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c09eb08dad
Import pending patches to support the upcoming Filogic platforms. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
47 lines
1.5 KiB
Diff
47 lines
1.5 KiB
Diff
From cf70b726c9844bb5d1ba4bc3c202c5ab3ba4d421 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Fri, 29 Jul 2022 11:15:35 +0800
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Subject: [PATCH 25/31] clk: mediatek: add CLK_XTAL support for clock driver
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This add CLK_XTAL macro and flag to mediatek clock driver common part,
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to make thi SoC that has clock directlly connect to XTAL working.
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/clk/mediatek/clk-mtk.c | 4 ++++
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drivers/clk/mediatek/clk-mtk.h | 3 ++-
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2 files changed, 6 insertions(+), 1 deletion(-)
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--- a/drivers/clk/mediatek/clk-mtk.c
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+++ b/drivers/clk/mediatek/clk-mtk.c
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@@ -296,6 +296,7 @@ static ulong mtk_topckgen_get_factor_rat
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
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break;
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+ case CLK_PARENT_XTAL:
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default:
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rate = priv->tree->xtal_rate;
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}
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@@ -314,6 +315,9 @@ static ulong mtk_infrasys_get_factor_rat
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent,
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priv->parent);
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break;
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+ case CLK_PARENT_XTAL:
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+ rate = priv->tree->xtal_rate;
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+ break;
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default:
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rate = mtk_clk_find_parent_rate(clk, fdiv->parent, NULL);
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}
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--- a/drivers/clk/mediatek/clk-mtk.h
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+++ b/drivers/clk/mediatek/clk-mtk.h
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@@ -29,7 +29,8 @@
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#define CLK_PARENT_APMIXED BIT(4)
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#define CLK_PARENT_TOPCKGEN BIT(5)
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#define CLK_PARENT_INFRASYS BIT(6)
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-#define CLK_PARENT_MASK GENMASK(6, 4)
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+#define CLK_PARENT_XTAL BIT(7)
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+#define CLK_PARENT_MASK GENMASK(7, 4)
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#define ETHSYS_HIFSYS_RST_CTRL_OFS 0x34
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