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c36de2e73a
Backport almost 50 commits from upstream Linux to improve thermal drivers for MediaTek SoCs and add new LVTS driver for MT7988. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
187 lines
5.0 KiB
Diff
187 lines
5.0 KiB
Diff
From 498e2f7a6e69dcbca24715de2b4b97569fdfeff4 Mon Sep 17 00:00:00 2001
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From: Balsam CHIHI <bchihi@baylibre.com>
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Date: Thu, 9 Feb 2023 11:56:24 +0100
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Subject: [PATCH] dt-bindings: thermal: mediatek: Add LVTS thermal controllers
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Add LVTS thermal controllers dt-binding definition for mt8192 and mt8195.
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Signed-off-by: Balsam CHIHI <bchihi@baylibre.com>
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Reviewed-by: Rob Herring <robh@kernel.org>
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Link: https://lore.kernel.org/r/20230209105628.50294-3-bchihi@baylibre.com
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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---
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.../thermal/mediatek,lvts-thermal.yaml | 142 ++++++++++++++++++
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.../thermal/mediatek,lvts-thermal.h | 19 +++
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2 files changed, 161 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
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create mode 100644 include/dt-bindings/thermal/mediatek,lvts-thermal.h
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml
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@@ -0,0 +1,142 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: MediaTek SoC Low Voltage Thermal Sensor (LVTS)
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+
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+maintainers:
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+ - Balsam CHIHI <bchihi@baylibre.com>
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+
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+description: |
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+ LVTS is a thermal management architecture composed of three subsystems,
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+ a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU),
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+ a Converter - Low Voltage Thermal Sensor converter (LVTS), and
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+ a Digital controller (LVTS_CTRL).
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+
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+properties:
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+ compatible:
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+ enum:
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+ - mediatek,mt8192-lvts-ap
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+ - mediatek,mt8192-lvts-mcu
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+ - mediatek,mt8195-lvts-ap
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+ - mediatek,mt8195-lvts-mcu
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+
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+ reg:
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+ maxItems: 1
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+
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+ interrupts:
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+ maxItems: 1
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+
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+ clocks:
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+ maxItems: 1
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+
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+ resets:
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+ maxItems: 1
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+ description: LVTS reset for clearing temporary data on AP/MCU.
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+
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+ nvmem-cells:
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+ minItems: 1
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+ items:
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+ - description: Calibration eFuse data 1 for LVTS
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+ - description: Calibration eFuse data 2 for LVTS
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+
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+ nvmem-cell-names:
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+ minItems: 1
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+ items:
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+ - const: lvts-calib-data-1
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+ - const: lvts-calib-data-2
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+
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+ "#thermal-sensor-cells":
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+ const: 1
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+
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+allOf:
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+ - $ref: thermal-sensor.yaml#
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+
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+ - if:
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+ properties:
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+ compatible:
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+ contains:
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+ enum:
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+ - mediatek,mt8192-lvts-ap
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+ - mediatek,mt8192-lvts-mcu
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+ then:
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+ properties:
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+ nvmem-cells:
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+ maxItems: 1
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+
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+ nvmem-cell-names:
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+ maxItems: 1
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+
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+ - if:
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+ properties:
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+ compatible:
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+ contains:
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+ enum:
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+ - mediatek,mt8195-lvts-ap
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+ - mediatek,mt8195-lvts-mcu
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+ then:
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+ properties:
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+ nvmem-cells:
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+ minItems: 2
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+
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+ nvmem-cell-names:
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+ minItems: 2
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+
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+required:
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+ - compatible
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+ - reg
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+ - interrupts
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+ - clocks
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+ - resets
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+ - nvmem-cells
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+ - nvmem-cell-names
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+ - "#thermal-sensor-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ #include <dt-bindings/interrupt-controller/arm-gic.h>
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+ #include <dt-bindings/clock/mt8195-clk.h>
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+ #include <dt-bindings/reset/mt8195-resets.h>
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+ #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
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+
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+ soc {
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+
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+ lvts_mcu: thermal-sensor@11278000 {
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+ compatible = "mediatek,mt8195-lvts-mcu";
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+ reg = <0 0x11278000 0 0x1000>;
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+ interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
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+ clocks = <&infracfg_ao CLK_INFRA_AO_THERM>;
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+ resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>;
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+ nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
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+ nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
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+ #thermal-sensor-cells = <1>;
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+ };
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+ };
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+
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+ thermal_zones: thermal-zones {
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+ cpu0-thermal {
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+ polling-delay = <1000>;
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+ polling-delay-passive = <250>;
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+ thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
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+
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+ trips {
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+ cpu0_alert: trip-alert {
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+ temperature = <85000>;
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+ hysteresis = <2000>;
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+ type = "passive";
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+ };
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+
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+ cpu0_crit: trip-crit {
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+ temperature = <100000>;
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+ hysteresis = <2000>;
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+ type = "critical";
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+ };
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+ };
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+ };
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+ };
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--- /dev/null
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+++ b/include/dt-bindings/thermal/mediatek,lvts-thermal.h
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@@ -0,0 +1,19 @@
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+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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+/*
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+ * Copyright (c) 2023 MediaTek Inc.
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+ * Author: Balsam CHIHI <bchihi@baylibre.com>
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+ */
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+
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+#ifndef __MEDIATEK_LVTS_DT_H
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+#define __MEDIATEK_LVTS_DT_H
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+
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+#define MT8195_MCU_BIG_CPU0 0
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+#define MT8195_MCU_BIG_CPU1 1
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+#define MT8195_MCU_BIG_CPU2 2
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+#define MT8195_MCU_BIG_CPU3 3
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+#define MT8195_MCU_LITTLE_CPU0 4
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+#define MT8195_MCU_LITTLE_CPU1 5
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+#define MT8195_MCU_LITTLE_CPU2 6
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+#define MT8195_MCU_LITTLE_CPU3 7
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+
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+#endif /* __MEDIATEK_LVTS_DT_H */
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