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659f4a13dd
With Linux 6.1 many of our downstream patches and out-of-tree files can be removed or at least replaced by backported upstream commits. Signed-off-by: Daniel Golle <daniel@makrotopia.org> [fix CMDLINE_OVERRIDE for arm64] Signed-off-by: Bjørn Mork <bjorn@mork.no>
98 lines
4.6 KiB
Diff
98 lines
4.6 KiB
Diff
From 3511004225ce917a4aa6e6ac61481ac60f08f401 Mon Sep 17 00:00:00 2001
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From: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Date: Fri, 20 Jan 2023 10:20:52 +0100
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Subject: [PATCH 06/15] clk: mediatek: clk-mt7986-topckgen: Properly keep some
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clocks enabled
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Instead of calling clk_prepare_enable() on a bunch of clocks at probe
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time, set the CLK_IS_CRITICAL flag to the same as these are required
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to be always on, and this is the right way of achieving that.
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Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
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Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
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Reviewed-by: Miles Chen <miles.chen@mediatek.com>
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Link: https://lore.kernel.org/r/20230120092053.182923-23-angelogioacchino.delregno@collabora.com
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Tested-by: Mingming Su <mingming.su@mediatek.com>
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Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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---
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drivers/clk/mediatek/clk-mt7986-topckgen.c | 46 +++++++++++-----------
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1 file changed, 24 insertions(+), 22 deletions(-)
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--- a/drivers/clk/mediatek/clk-mt7986-topckgen.c
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+++ b/drivers/clk/mediatek/clk-mt7986-topckgen.c
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@@ -202,16 +202,23 @@ static const struct mtk_mux top_muxes[]
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MUX_GATE_CLR_SET_UPD(CLK_TOP_F_26M_ADC_SEL, "f_26m_adc_sel",
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f_26m_adc_parents, 0x020, 0x024, 0x028, 16, 1, 23,
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0x1C0, 10),
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- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_SEL, "dramc_sel", f_26m_adc_parents,
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- 0x020, 0x024, 0x028, 24, 1, 31, 0x1C0, 11),
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+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_SEL, "dramc_sel",
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+ f_26m_adc_parents, 0x020, 0x024, 0x028,
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+ 24, 1, 31, 0x1C0, 11,
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+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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/* CLK_CFG_3 */
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- MUX_GATE_CLR_SET_UPD(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
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- dramc_md32_parents, 0x030, 0x034, 0x038, 0, 1, 7,
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- 0x1C0, 12),
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- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAXI_SEL, "sysaxi_sel", sysaxi_parents,
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- 0x030, 0x034, 0x038, 8, 2, 15, 0x1C0, 13),
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- MUX_GATE_CLR_SET_UPD(CLK_TOP_SYSAPB_SEL, "sysapb_sel", sysapb_parents,
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- 0x030, 0x034, 0x038, 16, 2, 23, 0x1C0, 14),
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+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_DRAMC_MD32_SEL, "dramc_md32_sel",
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+ dramc_md32_parents, 0x030, 0x034, 0x038,
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+ 0, 1, 7, 0x1C0, 12,
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+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAXI_SEL, "sysaxi_sel",
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+ sysaxi_parents, 0x030, 0x034, 0x038,
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+ 8, 2, 15, 0x1C0, 13,
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+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SYSAPB_SEL, "sysapb_sel",
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+ sysapb_parents, 0x030, 0x034, 0x038,
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+ 16, 2, 23, 0x1C0, 14,
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+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_ARM_DB_MAIN_SEL, "arm_db_main_sel",
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arm_db_main_parents, 0x030, 0x034, 0x038, 24, 1,
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31, 0x1C0, 15),
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@@ -234,9 +241,10 @@ static const struct mtk_mux top_muxes[]
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MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_325M_SEL, "sgm_325m_sel",
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sgm_325m_parents, 0x050, 0x054, 0x058, 8, 1, 15,
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0x1C0, 21),
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- MUX_GATE_CLR_SET_UPD(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
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- sgm_reg_parents, 0x050, 0x054, 0x058, 16, 1, 23,
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- 0x1C0, 22),
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+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_SGM_REG_SEL, "sgm_reg_sel",
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+ sgm_reg_parents, 0x050, 0x054, 0x058,
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+ 16, 1, 23, 0x1C0, 22,
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+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_A1SYS_SEL, "a1sys_sel", a1sys_parents,
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0x050, 0x054, 0x058, 24, 1, 31, 0x1C0, 23),
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/* CLK_CFG_6 */
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@@ -252,9 +260,10 @@ static const struct mtk_mux top_muxes[]
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f_26m_adc_parents, 0x060, 0x064, 0x068, 24, 1, 31,
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0x1C0, 27),
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/* CLK_CFG_7 */
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- MUX_GATE_CLR_SET_UPD(CLK_TOP_F26M_SEL, "csw_f26m_sel",
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- f_26m_adc_parents, 0x070, 0x074, 0x078, 0, 1, 7,
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- 0x1C0, 28),
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+ MUX_GATE_CLR_SET_UPD_FLAGS(CLK_TOP_F26M_SEL, "csw_f26m_sel",
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+ f_26m_adc_parents, 0x070, 0x074, 0x078,
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+ 0, 1, 7, 0x1C0, 28,
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+ CLK_IS_CRITICAL | CLK_SET_RATE_PARENT),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_AUD_L_SEL, "aud_l_sel", aud_l_parents,
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0x070, 0x074, 0x078, 8, 2, 15, 0x1C0, 29),
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MUX_GATE_CLR_SET_UPD(CLK_TOP_A_TUNER_SEL, "a_tuner_sel",
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@@ -307,13 +316,6 @@ static int clk_mt7986_topckgen_probe(str
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ARRAY_SIZE(top_muxes), node,
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&mt7986_clk_lock, clk_data);
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- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAXI_SEL]->clk);
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- clk_prepare_enable(clk_data->hws[CLK_TOP_SYSAPB_SEL]->clk);
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- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_SEL]->clk);
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- clk_prepare_enable(clk_data->hws[CLK_TOP_DRAMC_MD32_SEL]->clk);
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- clk_prepare_enable(clk_data->hws[CLK_TOP_F26M_SEL]->clk);
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- clk_prepare_enable(clk_data->hws[CLK_TOP_SGM_REG_SEL]->clk);
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-
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r) {
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