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14722242af
The commit 7160820d742a ("phy: rockchip: naneng-combphy: fix phy reset")
was backported to kernel 6.6 branch by upstream, however the correspond
dtsi fixes was not, resulting the following error:
```
[ 0.225521] rockchip-naneng-combphy fe830000.phy: error -ENOENT: failed to get phy reset
[ 0.227467] rockchip-naneng-combphy fe840000.phy: error -ENOENT: failed to get phy reset
```
So backport the dtsi fixes here manually.
Fixes: 89b2356b8c ("kernel: bump 6.6 to 6.6.69")
Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
Link: https://github.com/openwrt/openwrt/pull/17468
Signed-off-by: Robert Marko <robimarko@gmail.com>
(cherry picked from commit 8a477bafb4)
45 lines
1.6 KiB
Diff
45 lines
1.6 KiB
Diff
From 8b9c12757f919157752646faf3821abf2b7d2a64 Mon Sep 17 00:00:00 2001
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From: Chukun Pan <amadeus@jmu.edu.cn>
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Date: Fri, 22 Nov 2024 15:30:05 +0800
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Subject: [PATCH] arm64: dts: rockchip: add reset-names for combphy on rk3568
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The reset-names of combphy are missing, add it.
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Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
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Fixes: fd3ac6e80497 ("dt-bindings: phy: rockchip: rk3588 has two reset lines")
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Link: https://lore.kernel.org/r/20241122073006.99309-1-amadeus@jmu.edu.cn
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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arch/arm64/boot/dts/rockchip/rk3568.dtsi | 1 +
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arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 2 ++
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2 files changed, 3 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
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@@ -223,6 +223,7 @@
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assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_PIPEPHY0>;
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+ reset-names = "phy";
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rockchip,pipe-grf = <&pipegrf>;
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rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
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#phy-cells = <1>;
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--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
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@@ -1747,6 +1747,7 @@
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assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_PIPEPHY1>;
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+ reset-names = "phy";
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rockchip,pipe-grf = <&pipegrf>;
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rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
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#phy-cells = <1>;
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@@ -1763,6 +1764,7 @@
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assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
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assigned-clock-rates = <100000000>;
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resets = <&cru SRST_PIPEPHY2>;
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+ reset-names = "phy";
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rockchip,pipe-grf = <&pipegrf>;
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rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
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#phy-cells = <1>;
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