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ba6096d04b
OpenWRT's developer guide prefers having actual patches so they an be sent upstream more easily. However, in this case, Adding proper fields also allows for `git am` to properly function. Some of these patches are quite old, and lack much traceable history. This commit tries to rectify that, by digging in the history to find where and how it was first added. It is by no means perfect and also shows some patches that should have been long gone. Signed-off-by: Olliver Schinagl <oliver@schinagl.nl>
31 lines
1.2 KiB
Diff
31 lines
1.2 KiB
Diff
From: David Bauer <mail@david-bauer.net>
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Subject: [PATCH] ath79: force SGMII SerDes mode to MAC operation
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The mode on the SGMII SerDes on the QCA9563 is 1000 Base-X by default.
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This only allows for 1000 Mbit/s links, however when used with an SGMII
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PHY in 100 Mbit/s link mode, the link remains dead.
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This strictly has nothing to do with the SerDes calibration, however it
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is done at the same point in the QCA reference U-Boot which is the
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blueprint for everything happening here. As the current state is more or
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less a hack, this should be fine.
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This fixes the issues outlined above on a TP-Link EAP-225 Outdoor.
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Reported-by: Tom Herbers <freifunk@tomherbers.de>
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Tested-by: Tom Herbers <freifunk@tomherbers.de>
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Submitted-by: David Bauer <mail@david-bauer.net>
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---
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arch/mips/include/asm/mach-ath79/ar71xx_regs.h | 1 +
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1 files changed, 1 insertion(+)
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -1376,5 +1376,6 @@
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#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT 0
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#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK 0x7
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+#define QCA956X_SGMII_CONFIG_MODE_CTRL_SGMII_MAC 0x2
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#endif /* __ASM_MACH_AR71XX_REGS_H */
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