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BCM6318 has a special initialization sequence which involves touching PLL control registers in the USBH_PRIV register space, as well as toggling a bit the Simulation control register. Signed-off-by: Florian Fainelli <florian@openwrt.org> SVN-Revision: 39302
52 lines
1.7 KiB
Diff
52 lines
1.7 KiB
Diff
--- a/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/pci_ath9k_fixup.h
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@@ -2,6 +2,7 @@
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#define _PCI_ATH9K_FIXUP
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-void pci_enable_ath9k_fixup(unsigned slot, u32 offset) __init;
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+void pci_enable_ath9k_fixup(unsigned slot, u32 offset,
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+ unsigned endian_check) __init;
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#endif /* _PCI_ATH9K_FIXUP */
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--- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
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@@ -19,6 +19,7 @@
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struct ath9k_caldata {
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unsigned int slot;
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u32 caldata_offset;
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+ unsigned int endian_check:1;
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};
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/*
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--- a/arch/mips/bcm63xx/pci-ath9k-fixup.c
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+++ b/arch/mips/bcm63xx/pci-ath9k-fixup.c
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@@ -174,12 +174,14 @@ static void ath9k_pci_fixup(struct pci_d
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATHEROS, PCI_ANY_ID, ath9k_pci_fixup);
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-void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset)
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+void __init pci_enable_ath9k_fixup(unsigned slot, u32 offset,
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+ unsigned endian_check)
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{
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if (ath9k_num_fixups >= ARRAY_SIZE(ath9k_fixups))
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return;
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ath9k_fixups[ath9k_num_fixups].slot = slot;
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+ ath9k_fixups[ath9k_num_fixups].pdata.endian_check = endian_check;
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if (!bcm63xx_read_eeprom(ath9k_fixups[ath9k_num_fixups].pdata.eeprom_data, offset))
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return;
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--- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
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+++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
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@@ -1058,7 +1058,8 @@ int __init board_register_devices(void)
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/* register any fixups */
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for (i = 0; i < board.has_caldata; i++)
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- pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset);
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+ pci_enable_ath9k_fixup(board.caldata[i].slot, board.caldata[i].caldata_offset,
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+ board.caldata[i].endian_check);
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return 0;
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}
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