mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 10:39:04 +00:00
d40756563c
Let's pick a bunch of useful phylink changes which allow us to keep drivers in sync with mainline Linux. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
77 lines
2.6 KiB
Diff
77 lines
2.6 KiB
Diff
From aa8b6bd2b1f235b262bd27f317a0516f196c2c6a Mon Sep 17 00:00:00 2001
|
|
From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
|
|
Date: Tue, 23 May 2023 11:15:58 +0100
|
|
Subject: [PATCH 18/21] net: phylink: add function to resolve clause 73
|
|
negotiation
|
|
|
|
Add a function to resolve clause 73 negotiation according to the
|
|
priority resolution function described in clause 73.3.6.
|
|
|
|
Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
|
|
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
|
|
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
|
|
---
|
|
drivers/net/phy/phylink.c | 39 +++++++++++++++++++++++++++++++++++++++
|
|
include/linux/phylink.h | 2 ++
|
|
2 files changed, 41 insertions(+)
|
|
|
|
--- a/drivers/net/phy/phylink.c
|
|
+++ b/drivers/net/phy/phylink.c
|
|
@@ -3212,6 +3212,45 @@ static const struct sfp_upstream_ops sfp
|
|
|
|
/* Helpers for MAC drivers */
|
|
|
|
+static struct {
|
|
+ int bit;
|
|
+ int speed;
|
|
+} phylink_c73_priority_resolution[] = {
|
|
+ { ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, SPEED_100000 },
|
|
+ { ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, SPEED_100000 },
|
|
+ /* 100GBASE-KP4 and 100GBASE-CR10 not supported */
|
|
+ { ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, SPEED_40000 },
|
|
+ { ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, SPEED_40000 },
|
|
+ { ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, SPEED_10000 },
|
|
+ { ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, SPEED_10000 },
|
|
+ /* 5GBASE-KR not supported */
|
|
+ { ETHTOOL_LINK_MODE_2500baseX_Full_BIT, SPEED_2500 },
|
|
+ { ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, SPEED_1000 },
|
|
+};
|
|
+
|
|
+void phylink_resolve_c73(struct phylink_link_state *state)
|
|
+{
|
|
+ int i;
|
|
+
|
|
+ for (i = 0; i < ARRAY_SIZE(phylink_c73_priority_resolution); i++) {
|
|
+ int bit = phylink_c73_priority_resolution[i].bit;
|
|
+ if (linkmode_test_bit(bit, state->advertising) &&
|
|
+ linkmode_test_bit(bit, state->lp_advertising))
|
|
+ break;
|
|
+ }
|
|
+
|
|
+ if (i < ARRAY_SIZE(phylink_c73_priority_resolution)) {
|
|
+ state->speed = phylink_c73_priority_resolution[i].speed;
|
|
+ state->duplex = DUPLEX_FULL;
|
|
+ } else {
|
|
+ /* negotiation failure */
|
|
+ state->link = false;
|
|
+ }
|
|
+
|
|
+ phylink_resolve_an_pause(state);
|
|
+}
|
|
+EXPORT_SYMBOL_GPL(phylink_resolve_c73);
|
|
+
|
|
static void phylink_decode_c37_word(struct phylink_link_state *state,
|
|
uint16_t config_reg, int speed)
|
|
{
|
|
--- a/include/linux/phylink.h
|
|
+++ b/include/linux/phylink.h
|
|
@@ -656,6 +656,8 @@ int phylink_mii_c22_pcs_config(struct md
|
|
const unsigned long *advertising);
|
|
void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
|
|
|
|
+void phylink_resolve_c73(struct phylink_link_state *state);
|
|
+
|
|
void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
|
|
struct phylink_link_state *state);
|
|
|