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df8e6be59a
This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
111 lines
1.8 KiB
Plaintext
111 lines
1.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "realtek,rtl838x-soc";
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reg = <0xbb000000 0xa000>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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frequency = <500000000>;
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cpu@0 {
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compatible = "mips,mips4KEc";
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reg = <0>;
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};
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x8000000>;
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};
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chosen {
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bootargs = "console=ttyS0,38400";
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};
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cpuintc: cpuintc {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "rtl838x,icu";
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reg = <0xb8003000 0x20>;
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};
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spi0: spi@b8001200 {
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status = "okay";
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compatible = "realtek,rtl838x-nor";
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reg = <0xb8001200 0x100>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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uart0: uart@b8002000 {
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status = "disabled";
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compatible = "ns16550a";
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reg = <0xb8002000 0x100>;
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clock-frequency = <200000000>;
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interrupts = <31>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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uart1: uart@b8002100 {
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status = "okay";
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compatible = "ns16550a";
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reg = <0xb8002100 0x100>;
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clock-frequency = <200000000>;
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interrupt-parent = <&cpuintc>;
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interrupts = <30>;
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reg-io-width = <1>;
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reg-shift = <2>;
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fifo-size = <1>;
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no-loopback-test;
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};
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gpio0: gpio-controller@b8003500 {
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compatible = "realtek,rtl838x-gpio";
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reg = <0xb8003500 0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <23>;
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};
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ethernet0: ethernet@bb00a300 {
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status = "okay";
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compatible = "realtek,rtl838x-eth";
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reg = <0xbb00a300 0x100>;
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interrupt-parent = <&cpuintc>;
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interrupts = <24>;
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#interrupt-cells = <1>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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switch0: switch@bb000000 {
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status = "okay";
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compatible = "realtek,rtl838x-switch";
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};
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};
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