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df8e6be59a
This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
222 lines
3.5 KiB
Plaintext
222 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later
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/dts-v1/;
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#include "rtl838x.dtsi"
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/gpio/gpio.h>
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/ {
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compatible = "allnet,all-sg8208m", "realtek,rtl838x-soc";
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model = "ALLNET ALL-SG8208M";
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aliases {
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led-boot = &led_sys;
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led-failsafe = &led_sys;
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led-running = &led_sys;
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led-upgrade = &led_sys;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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keys {
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compatible = "gpio-keys-polled";
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poll-interval = <20>;
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reset {
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label = "reset";
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gpios = <&gpio0 67 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_sys: sys {
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label = "all-sg8208m:green:sys";
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gpios = <&gpio0 47 GPIO_ACTIVE_HIGH>;
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};
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// GPIO 25: power on/off all port leds
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};
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};
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&gpio0 {
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indirect-access-bus-id = <0>;
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x80000 0x10000>;
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read-only;
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};
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partition@90000 {
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label = "u-boot-env2";
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reg = <0x90000 0x10000>;
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read-only;
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};
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partition@a0000 {
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label = "jffs";
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reg = <0xa0000 0x100000>;
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};
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partition@1a0000 {
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label = "jffs2";
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reg = <0x1a0000 0x100000>;
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};
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partition@2a0000 {
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label = "firmware";
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reg = <0x2a0000 0xd60000>;
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compatible = "allnet,uimage";
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};
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};
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};
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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/* Internal phy */
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phy8: ethernet-phy@8 {
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reg = <8>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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phy9: ethernet-phy@9 {
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reg = <9>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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phy10: ethernet-phy@10 {
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reg = <10>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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phy11: ethernet-phy@11 {
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reg = <11>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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phy12: ethernet-phy@12 {
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reg = <12>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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phy13: ethernet-phy@13 {
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reg = <13>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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phy14: ethernet-phy@14 {
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reg = <14>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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phy15: ethernet-phy@15 {
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reg = <15>;
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compatible = "ethernet-phy-ieee802.3-c22";
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};
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <8>;
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label = "lan1";
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phy-handle = <&phy8>;
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phy-mode = "internal";
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};
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port@1 {
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reg = <9>;
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label = "lan2";
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phy-handle = <&phy9>;
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phy-mode = "internal";
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};
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port@2 {
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reg = <10>;
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label = "lan3";
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phy-handle = <&phy10>;
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phy-mode = "internal";
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};
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port@3 {
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reg = <11>;
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label = "lan4";
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phy-handle = <&phy11>;
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phy-mode = "internal";
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};
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port@4 {
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reg = <12>;
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label = "lan5";
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phy-handle = <&phy12>;
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phy-mode = "internal";
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};
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port@5 {
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reg = <13>;
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label = "lan6";
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phy-handle = <&phy13>;
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phy-mode = "internal";
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};
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port@6 {
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reg = <14>;
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label = "lan7";
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phy-handle = <&phy14>;
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phy-mode = "internal";
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};
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port@7 {
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reg = <15>;
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label = "lan8";
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phy-handle = <&phy15>;
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phy-mode = "internal";
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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