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https://github.com/openwrt/openwrt.git
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79abb8f140
Bump & refresh patches for all 4.4 targets. Compile & run tested: ar71xx Archer C7 v2 Signed-off-by: Kevin Darbyshire-Bryant <kevin@darbyshire-bryant.me.uk>
102 lines
2.5 KiB
Diff
102 lines
2.5 KiB
Diff
--- a/arch/mips/ath79/dev-usb.c
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+++ b/arch/mips/ath79/dev-usb.c
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@@ -37,6 +37,8 @@ static struct usb_ehci_pdata ath79_ehci_
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static struct usb_ehci_pdata ath79_ehci_pdata_v2 = {
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.caps_offset = 0x100,
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.has_tt = 1,
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+ .qca_force_host_mode = 1,
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+ .qca_force_16bit_ptw = 1,
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};
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static void __init ath79_usb_register(const char *name, int id,
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@@ -159,6 +161,9 @@ static void __init ar913x_usb_setup(void
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ath79_device_reset_clear(AR913X_RESET_USB_PHY);
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mdelay(10);
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+ ath79_ehci_pdata_v2.qca_force_host_mode = 0;
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+ ath79_ehci_pdata_v2.qca_force_16bit_ptw = 0;
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+
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ath79_usb_register("ehci-platform", -1,
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AR913X_EHCI_BASE, AR913X_EHCI_SIZE,
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ATH79_CPU_IRQ(3),
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@@ -182,14 +187,34 @@ static void __init ar933x_usb_setup(void
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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-static void __init ar934x_usb_setup(void)
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+static void enable_tx_tx_idp_violation_fix(unsigned base)
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{
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- u32 bootstrap;
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+ void __iomem *phy_reg;
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+ u32 t;
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+
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+ phy_reg = ioremap(base, 4);
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+ if (!phy_reg)
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+ return;
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+
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+ t = ioread32(phy_reg);
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+ t &= ~0xff;
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+ t |= 0x58;
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+ iowrite32(t, phy_reg);
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+
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+ iounmap(phy_reg);
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+}
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- bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
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- if (bootstrap & AR934X_BOOTSTRAP_USB_MODE_DEVICE)
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+static void ar934x_usb_reset_notifier(struct platform_device *pdev)
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+{
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+ if (pdev->id != -1)
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return;
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+ enable_tx_tx_idp_violation_fix(0x18116c94);
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+ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n");
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+}
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+
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+static void __init ar934x_usb_setup(void)
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+{
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ath79_device_reset_set(AR934X_RESET_USBSUS_OVERRIDE);
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udelay(1000);
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@@ -202,14 +227,40 @@ static void __init ar934x_usb_setup(void
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ath79_device_reset_clear(AR934X_RESET_USB_HOST);
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udelay(1000);
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+ if (ath79_soc_rev >= 3)
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+ ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier;
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+
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ath79_usb_register("ehci-platform", -1,
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AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
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ATH79_CPU_IRQ(3),
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&ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
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}
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+static void qca955x_usb_reset_notifier(struct platform_device *pdev)
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+{
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+ u32 base;
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+
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+ switch (pdev->id) {
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+ case 0:
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+ base = 0x18116c94;
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+ break;
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+
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+ case 1:
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+ base = 0x18116e54;
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+ break;
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+
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+ default:
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+ return;
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+ }
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+
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+ enable_tx_tx_idp_violation_fix(base);
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+ dev_info(&pdev->dev, "TX-TX IDP fix enabled\n");
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+}
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+
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static void __init qca955x_usb_setup(void)
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{
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+ ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier;
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+
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ath79_usb_register("ehci-platform", 0,
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QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
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ATH79_IP3_IRQ(0),
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