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be71e16630
Backport H616 DVFS support from linux-next. Tested on the Orange Pi Zero 3 (H618 SoC). Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Link: https://github.com/openwrt/openwrt/pull/15600 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
123 lines
3.5 KiB
Diff
123 lines
3.5 KiB
Diff
From e2e2dcd2e944fe6167cb731864f8a1343f1bbee7 Mon Sep 17 00:00:00 2001
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From: Martin Botka <martin.botka@somainline.org>
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Date: Thu, 18 Apr 2024 16:44:06 +0100
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Subject: [PATCH] cpufreq: sun50i: Add H616 support
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The Allwinner H616/H618 SoCs have different OPP tables per SoC version
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and die revision. The SoC version is stored in NVMEM, as before, though
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encoded differently. The die revision is in a different register, in the
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SRAM controller. Firmware already exports that value in a standardised
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way, through the SMCCC SoCID mechanism. We need both values, as some chips
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have the same SoC version, but they don't support the same frequencies and
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they get differentiated by the die revision.
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Add the new compatible string and tie the new translation function to
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it. This mechanism not only covers the original H616 SoC, but also its
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very close sibling SoCs H618 and H700, so add them to the list as well.
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Signed-off-by: Martin Botka <martin.botka@somainline.org>
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Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
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---
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drivers/cpufreq/sun50i-cpufreq-nvmem.c | 67 ++++++++++++++++++++++++++
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1 file changed, 67 insertions(+)
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--- a/drivers/cpufreq/sun50i-cpufreq-nvmem.c
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+++ b/drivers/cpufreq/sun50i-cpufreq-nvmem.c
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@@ -10,6 +10,7 @@
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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+#include <linux/arm-smccc.h>
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#include <linux/cpu.h>
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#include <linux/module.h>
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#include <linux/nvmem-consumer.h>
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@@ -46,14 +47,77 @@ static u32 sun50i_h6_efuse_xlate(u32 spe
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return 0;
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}
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+static int get_soc_id_revision(void)
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+{
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+#ifdef CONFIG_HAVE_ARM_SMCCC_DISCOVERY
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+ return arm_smccc_get_soc_id_revision();
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+#else
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+ return SMCCC_RET_NOT_SUPPORTED;
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+#endif
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+}
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+
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+/*
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+ * Judging by the OPP tables in the vendor BSP, the quality order of the
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+ * returned speedbin index is 4 -> 0/2 -> 3 -> 1, from worst to best.
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+ * 0 and 2 seem identical from the OPP tables' point of view.
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+ */
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+static u32 sun50i_h616_efuse_xlate(u32 speedbin)
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+{
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+ int ver_bits = get_soc_id_revision();
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+ u32 value = 0;
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+
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+ switch (speedbin & 0xffff) {
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+ case 0x2000:
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+ value = 0;
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+ break;
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+ case 0x2400:
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+ case 0x7400:
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+ case 0x2c00:
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+ case 0x7c00:
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+ if (ver_bits != SMCCC_RET_NOT_SUPPORTED && ver_bits <= 1) {
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+ /* ic version A/B */
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+ value = 1;
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+ } else {
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+ /* ic version C and later version */
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+ value = 2;
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+ }
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+ break;
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+ case 0x5000:
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+ case 0x5400:
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+ case 0x6000:
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+ value = 3;
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+ break;
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+ case 0x5c00:
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+ value = 4;
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+ break;
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+ case 0x5d00:
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+ value = 0;
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+ break;
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+ default:
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+ pr_warn("sun50i-cpufreq-nvmem: unknown speed bin 0x%x, using default bin 0\n",
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+ speedbin & 0xffff);
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+ value = 0;
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+ break;
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+ }
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+
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+ return value;
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+}
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+
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static struct sunxi_cpufreq_data sun50i_h6_cpufreq_data = {
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.efuse_xlate = sun50i_h6_efuse_xlate,
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};
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+static struct sunxi_cpufreq_data sun50i_h616_cpufreq_data = {
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+ .efuse_xlate = sun50i_h616_efuse_xlate,
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+};
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+
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static const struct of_device_id cpu_opp_match_list[] = {
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{ .compatible = "allwinner,sun50i-h6-operating-points",
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.data = &sun50i_h6_cpufreq_data,
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},
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+ { .compatible = "allwinner,sun50i-h616-operating-points",
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+ .data = &sun50i_h616_cpufreq_data,
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+ },
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{}
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};
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@@ -230,6 +294,9 @@ static struct platform_driver sun50i_cpu
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static const struct of_device_id sun50i_cpufreq_match_list[] = {
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{ .compatible = "allwinner,sun50i-h6" },
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+ { .compatible = "allwinner,sun50i-h616" },
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+ { .compatible = "allwinner,sun50i-h618" },
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+ { .compatible = "allwinner,sun50i-h700" },
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{}
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};
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MODULE_DEVICE_TABLE(of, sun50i_cpufreq_match_list);
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