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be0639063a
Merged upstream: bcm27xx/patches-5.4/950-1014-Revert-mailbox-avoid-timer-start-from-callback.patch generic/backport-5.4/080-wireguard-0021-crypto-blake2s-generic-C-library-implementation-and-.patch Manually adapted: layerscape/patches-5.4/801-audio-0005-Revert-ASoC-fsl_sai-Add-support-for-SAI-new-version.patch oxnas/patches-5.4/100-oxnas-clk-plla-pllb.patch Compile-tested: lantiq/xrx200 Run-tested: lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
38 lines
1.3 KiB
Diff
38 lines
1.3 KiB
Diff
From ca49d3e4820704bfc3d2b48f59238d26a584602d Mon Sep 17 00:00:00 2001
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From: Alex Marginean <alexandru.marginean@nxp.com>
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Date: Fri, 20 Sep 2019 19:37:19 +0300
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Subject: [PATCH] drivers: net: phy: aquantia: enable USX AN for USXGMII
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protocol
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Depending on FW defaults USX AN in AQR PHY must be explicitly enabled when
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using USXGMII. Enable it based on interface type.
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Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
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---
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drivers/net/phy/aquantia_main.c | 7 +++++++
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1 file changed, 7 insertions(+)
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--- a/drivers/net/phy/aquantia_main.c
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+++ b/drivers/net/phy/aquantia_main.c
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@@ -33,6 +33,9 @@
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII 6
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#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII 10
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+#define MDIO_PHYXS_VEND_PROV2 0xC441
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+#define MDIO_PHYXS_VEND_PROV2_USX_AN BIT(3)
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+
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#define MDIO_AN_VEND_PROV 0xc400
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#define MDIO_AN_VEND_PROV_1000BASET_FULL BIT(15)
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#define MDIO_AN_VEND_PROV_1000BASET_HALF BIT(14)
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@@ -323,6 +326,10 @@ static int aqr_config_aneg_set_prot(stru
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aquantia_syscfg[if_type].syscfg);
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}
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+ if (if_type == PHY_INTERFACE_MODE_USXGMII)
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+ phy_write_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_PROV2,
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+ MDIO_PHYXS_VEND_PROV2_USX_AN);
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+
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/* wake PHY back up */
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phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GLOBAL_SC, 0);
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mdelay(10);
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