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e5aa498acb
Fixes CVE-2020-10757 via upstream commit df4988aa1c96 ("mm: Fix mremap
not considering huge pmd devmap").
Resolved merge conflict in the following patches:
bcm27xx: 950-0128-gpiolib-Don-t-prevent-IRQ-usage-of-output-GPIOs.patch
Refreshed patches, removed upstreamed patch:
generic: 751-v5.8-net-dsa-mt7530-set-CPU-port-to-fallback-mode.patch
generic: 754-v5.7-net-dsa-mt7530-fix-roaming-from-DSA-user-ports.patch
Run tested: qemu-x86-64
Build tested: x86/64, imx6, sunxi/a53
Signed-off-by: Petr Štetiar <ynezz@true.cz>
55 lines
1.6 KiB
Diff
55 lines
1.6 KiB
Diff
From d2cf2f91ba5b6d7696b1870e28017a3e1a7a1bb8 Mon Sep 17 00:00:00 2001
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From: Tim Harvey <tharvey@gateworks.com>
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Date: Fri, 28 Feb 2020 11:46:07 -0800
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Subject: [PATCH] ARM: dts: imx6qdl-gw5910: add CC1352 UART
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The GW5910-C revision adds a TI CC1352 connected to IMX UART4
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Signed-off-by: Tim Harvey <tharvey@gateworks.com>
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Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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---
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arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 25 +++++++++++++++++++++++++
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1 file changed, 25 insertions(+)
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--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
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+++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
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@@ -220,6 +220,14 @@
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status = "okay";
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};
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+/* cc1352 */
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+&uart3 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pinctrl_uart3>;
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+ uart-has-rtscts;
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+ status = "okay";
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+};
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+
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/* Sterling-LWB Bluetooth */
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&uart4 {
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pinctrl-names = "default";
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@@ -411,6 +419,23 @@
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>;
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};
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+ pinctrl_uart3: uart3grp {
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+ fsl,pins = <
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+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
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+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
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+ MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
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+ MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
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+ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
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+ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
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+ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
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+ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
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+ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
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+ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
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+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
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+ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
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+ >;
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+ };
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+
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pinctrl_uart4: uart4grp {
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fsl,pins = <
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MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
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