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a2950fabd4
This makes the PCI bus topology more standard for devices behind a bridge Signed-off-by: Tim Harvey <tharvey@gateworks.com> SVN-Revision: 35079
28 lines
879 B
Diff
28 lines
879 B
Diff
--- a/arch/arm/mach-cns3xxx/pcie.c
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+++ b/arch/arm/mach-cns3xxx/pcie.c
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@@ -79,9 +79,11 @@ static void __iomem *cns3xxx_pci_cfg_bas
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* the first device on the same bus as the CNS PCI bridge.
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*/
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if (busno == 0) {
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- if (slot > 1)
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+ if (slot > 0)
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return NULL;
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type = slot;
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+ } else if (busno == 1) {
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+ type = CNS3XXX_CFG0_TYPE;
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} else {
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type = CNS3XXX_CFG1_TYPE;
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}
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@@ -428,8 +430,9 @@ static void __init cns3xxx_pcie_hw_init(
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if (!cnspci->linked)
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return;
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- /* Set Device Max_Read_Request_Size to 128 byte */
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- devfn = PCI_DEVFN(1, 0);
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+ /* Configure Root Complex: Set Device Max_Read_Request_Size to 128 byte */
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+ bus.number = 1;
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+ devfn = PCI_DEVFN(0, 0);
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pos = pci_bus_find_capability(&bus, devfn, PCI_CAP_ID_EXP);
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pci_bus_read_config_word(&bus, devfn, pos + PCI_EXP_DEVCTL, &dc);
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dc &= ~(0x3 << 12); /* Clear Device Control Register [14:12] */
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