mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 22:47:56 +00:00
97 lines
2.7 KiB
Diff
97 lines
2.7 KiB
Diff
--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -373,6 +373,7 @@ config ARCH_CNS3XXX
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select MIGHT_HAVE_PCI
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select PCI_DOMAINS if PCI
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select HAVE_SMP
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+ select FIQ
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help
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Support for Cavium Networks CNS3XXX platform.
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--- a/arch/arm/kernel/fiq.c
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+++ b/arch/arm/kernel/fiq.c
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@@ -49,6 +49,8 @@
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static unsigned long no_fiq_insn;
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+unsigned int fiq_number[2] = {0, 0};
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+
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/* Default reacquire function
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* - we always relinquish FIQ control
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* - we always reacquire FIQ control
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@@ -70,9 +72,12 @@ static struct fiq_handler *current_fiq =
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int show_fiq_list(struct seq_file *p, int prec)
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{
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- if (current_fiq != &default_owner)
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- seq_printf(p, "%*s: %s\n", prec, "FIQ",
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- current_fiq->name);
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+ if (current_fiq != &default_owner) {
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+ seq_printf(p, "%*s: ", prec, "FIQ");
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+ seq_printf(p, "%10u ", fiq_number[0]);
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+ seq_printf(p, "%10u ", fiq_number[1]);
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+ seq_printf(p, " %s\n", current_fiq->name);
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+ }
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return 0;
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}
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--- a/arch/arm/kernel/smp.c
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+++ b/arch/arm/kernel/smp.c
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@@ -400,13 +400,13 @@ void show_ipi_list(struct seq_file *p, i
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unsigned int cpu, i;
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for (i = 0; i < NR_IPI; i++) {
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- seq_printf(p, "%*s%u: ", prec - 1, "IPI", i);
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+ seq_printf(p, "%*s%u:", prec - 1, "IPI", i);
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for_each_present_cpu(cpu)
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seq_printf(p, "%10u ",
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__get_irq_stat(cpu, ipi_irqs[i]));
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- seq_printf(p, " %s\n", ipi_types[i]);
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+ seq_printf(p, " %s\n", ipi_types[i]);
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}
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}
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--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -1,6 +1,6 @@
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obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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-obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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+obj-$(CONFIG_SMP) += platsmp.o headsmp.o cns3xxx_fiq.o
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obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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--- a/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/cns3xxx.h
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@@ -294,6 +294,7 @@
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#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100)
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#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100)
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+#define MISC_FIQ_CPU(x) MISC_MEM_MAP(0xA58 - (x) * 0x4)
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/*
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* Power management and clock control
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*/
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--- a/arch/arm/mach-cns3xxx/include/mach/irqs.h
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+++ b/arch/arm/mach-cns3xxx/include/mach/irqs.h
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@@ -14,6 +14,7 @@
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#define IRQ_LOCALTIMER 29
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#define IRQ_LOCALWDOG 30
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#define IRQ_TC11MP_GIC_START 32
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+#define FIQ_START 0
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#include <mach/cns3xxx.h>
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--- a/arch/arm/mm/Kconfig
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+++ b/arch/arm/mm/Kconfig
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@@ -793,7 +793,7 @@ config NEEDS_SYSCALL_FOR_CMPXCHG
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config DMA_CACHE_RWFO
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bool "Enable read/write for ownership DMA cache maintenance"
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- depends on CPU_V6K && SMP
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+ depends on CPU_V6K && SMP && !ARCH_CNS3XXX
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default y
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help
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The Snoop Control Unit on ARM11MPCore does not detect the
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