mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-28 09:39:00 +00:00
99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
23 lines
773 B
Diff
23 lines
773 B
Diff
From 7d47c62b378a4dbbf3e46a80c7b03966f8964da1 Mon Sep 17 00:00:00 2001
|
|
From: Samuel Holland <samuel@sholland.org>
|
|
Date: Fri, 12 Aug 2022 02:24:14 -0500
|
|
Subject: [PATCH 100/117] ARM: dts: sun8i: a33: Add DPHY interrupt
|
|
|
|
The DPHY has an interrupt line which is shared with the DSI controller.
|
|
|
|
Signed-off-by: Samuel Holland <samuel@sholland.org>
|
|
---
|
|
arch/arm/boot/dts/sun8i-a33.dtsi | 1 +
|
|
1 file changed, 1 insertion(+)
|
|
|
|
--- a/arch/arm/boot/dts/sun8i-a33.dtsi
|
|
+++ b/arch/arm/boot/dts/sun8i-a33.dtsi
|
|
@@ -278,6 +278,7 @@
|
|
dphy: d-phy@1ca1000 {
|
|
compatible = "allwinner,sun6i-a31-mipi-dphy";
|
|
reg = <0x01ca1000 0x1000>;
|
|
+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&ccu CLK_BUS_MIPI_DSI>,
|
|
<&ccu CLK_DSI_DPHY>;
|
|
clock-names = "bus", "mod";
|