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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
83 lines
2.1 KiB
Diff
83 lines
2.1 KiB
Diff
From 4c72279c90469971ca5ec627a76e50bf51bf076f Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 7 Aug 2022 10:59:29 -0500
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Subject: [PATCH 090/117] riscv: dts: allwinner: d1: Add DSI pipeline
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 49 ++++++++++++++++++++
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1 file changed, 49 insertions(+)
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--- a/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
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+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
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@@ -124,6 +124,14 @@
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#interrupt-cells = <3>;
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/omit-if-no-ref/
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+ dsi_4lane_pins: dsi-4lane-pins {
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+ pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5",
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+ "PD6", "PD7", "PD8", "PD9";
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+ drive-strength = <30>;
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+ function = "dsi";
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+ };
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+
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+ /omit-if-no-ref/
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i2c0_pb10_pins: i2c0-pb10-pins {
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pins = "PB10", "PB11";
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function = "i2c0";
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@@ -903,6 +911,40 @@
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};
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};
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+ dsi: dsi@5450000 {
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+ compatible = "allwinner,sun20i-d1-mipi-dsi",
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+ "allwinner,sun50i-a100-mipi-dsi";
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+ reg = <0x5450000 0x1000>;
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+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
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+ <&tcon_top CLK_TCON_TOP_DSI>;
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+ clock-names = "bus", "mod";
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+ resets = <&ccu RST_BUS_MIPI_DSI>;
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+ phys = <&dphy>;
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+ phy-names = "dphy";
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+ status = "disabled";
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ port {
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+ dsi_in_tcon_lcd0: endpoint {
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+ remote-endpoint = <&tcon_lcd0_out_dsi>;
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+ };
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+ };
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+ };
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+
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+ dphy: phy@5451000 {
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+ compatible = "allwinner,sun20i-d1-mipi-dphy",
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+ "allwinner,sun50i-a100-mipi-dphy";
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+ reg = <0x5451000 0x1000>;
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+ interrupts = <108 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_MIPI_DSI>,
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+ <&ccu CLK_MIPI_DSI>;
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+ clock-names = "bus", "mod";
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+ resets = <&ccu RST_BUS_MIPI_DSI>;
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+ #phy-cells = <0>;
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+ };
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+
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tcon_top: tcon-top@5460000 {
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compatible = "allwinner,sun20i-d1-tcon-top";
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reg = <0x5460000 0x1000>;
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@@ -1022,6 +1064,13 @@
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tcon_lcd0_out: port@1 {
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reg = <1>;
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+
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+ tcon_lcd0_out_dsi: endpoint@1 {
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+ reg = <1>;
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+ remote-endpoint = <&dsi_in_tcon_lcd0>;
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+ };
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};
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};
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};
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