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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
27 lines
931 B
Diff
27 lines
931 B
Diff
From 384e2ca3c049fe36f4e679fc76fcc8dfdc9297f9 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Wed, 27 Apr 2022 19:06:28 -0500
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Subject: [PATCH 051/117] iommu/sun50i: Ensure bypass is disabled
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The H6 variant of the hardware disables bypass by default. The D1
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variant of the hardware enables bypass for all masters by default.
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Since the driver expects bypass to be disabled, ensure that is the case.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/iommu/sun50i-iommu.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/iommu/sun50i-iommu.c
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+++ b/drivers/iommu/sun50i-iommu.c
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@@ -445,6 +445,8 @@ static int sun50i_iommu_enable(struct su
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spin_lock_irqsave(&iommu->iommu_lock, flags);
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+ iommu_write(iommu, IOMMU_BYPASS_REG, 0);
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+
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iommu_write(iommu, IOMMU_TTB_REG, sun50i_domain->dt_dma);
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iommu_write(iommu, IOMMU_TLB_PREFETCH_REG,
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IOMMU_TLB_PREFETCH_MASTER_ENABLE(0) |
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