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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
147 lines
3.6 KiB
Diff
147 lines
3.6 KiB
Diff
From 1f26c90ac9cbb60ff315c552368a3bca16562e51 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 10 Jul 2022 11:24:42 -0500
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Subject: [PATCH 032/117] riscv: dts: allwinner: Add Dongshan Nezha STU
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devicetree
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The 100ask Dongshan Nezha STU is a system-on-module that can be used
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standalone or with a carrier board. The SoM provides gigabit Ethernet,
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HDMI, a USB peripheral port, and WiFi/Bluetooth via an RTL8723DS chip.
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The "DIY" carrier board exposes almost every pin from the D1 SoC to 0.1"
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headers, but contains no digital circuitry, so it does not have its own
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devicetree.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/riscv/boot/dts/allwinner/Makefile | 1 +
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.../sun20i-d1-dongshan-nezha-stu.dts | 114 ++++++++++++++++++
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2 files changed, 115 insertions(+)
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create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
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--- a/arch/riscv/boot/dts/allwinner/Makefile
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+++ b/arch/riscv/boot/dts/allwinner/Makefile
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@@ -1,4 +1,5 @@
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# SPDX-License-Identifier: GPL-2.0
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+dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-dongshan-nezha-stu.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-480p.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-86-panel-720p.dtb
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dtb-$(CONFIG_ARCH_SUNXI) += sun20i-d1-lichee-rv-dock.dtb
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--- /dev/null
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+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1-dongshan-nezha-stu.dts
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@@ -0,0 +1,114 @@
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+// SPDX-License-Identifier: (GPL-2.0+ or MIT)
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+// Copyright (C) 2022 Samuel Holland <samuel@sholland.org>
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+
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+/dts-v1/;
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+
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+#include <dt-bindings/gpio/gpio.h>
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+#include <dt-bindings/leds/common.h>
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+
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+#include "sun20i-d1.dtsi"
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+#include "sun20i-d1-common-regulators.dtsi"
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+
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+/ {
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+ model = "Dongshan Nezha STU";
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+ compatible = "100ask,dongshan-nezha-stu", "allwinner,sun20i-d1";
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+
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+ aliases {
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+ ethernet0 = &emac;
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+ mmc0 = &mmc0;
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+ serial0 = &uart0;
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+ };
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+
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+ chosen {
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+ stdout-path = "serial0:115200n8";
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+ };
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+
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+ leds {
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+ compatible = "gpio-leds";
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+
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+ led-0 {
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+ color = <LED_COLOR_ID_GREEN>;
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+ function = LED_FUNCTION_STATUS;
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+ gpios = <&pio 2 1 GPIO_ACTIVE_HIGH>; /* PC1 */
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+ };
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+ };
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+
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+ reg_usbvbus: usbvbus {
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+ compatible = "regulator-fixed";
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+ regulator-name = "usbvbus";
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+ regulator-min-microvolt = <5000000>;
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+ regulator-max-microvolt = <5000000>;
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+ gpio = <&pio 3 19 GPIO_ACTIVE_HIGH>; /* PD19 */
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+ enable-active-high;
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+ vin-supply = <®_vcc>;
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+ };
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+
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+ /*
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+ * This regulator is PWM-controlled, but the PWM controller is not
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+ * yet supported, so fix the regulator to its default voltage.
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+ */
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+ reg_vdd_cpu: vdd-cpu {
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+ compatible = "regulator-fixed";
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+ regulator-name = "vdd-cpu";
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+ regulator-min-microvolt = <1100000>;
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+ regulator-max-microvolt = <1100000>;
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+ vin-supply = <®_vcc>;
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+ };
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+};
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+
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+&cpu0 {
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+ cpu-supply = <®_vdd_cpu>;
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+};
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+
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+&ehci0 {
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+ status = "okay";
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+};
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+
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+&emac {
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+ pinctrl-0 = <&rgmii_pe_pins>;
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+ pinctrl-names = "default";
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+ phy-handle = <&ext_rgmii_phy>;
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+ phy-mode = "rgmii-id";
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+ phy-supply = <®_vcc_3v3>;
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+ status = "okay";
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+};
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+
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+&mdio {
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+ ext_rgmii_phy: ethernet-phy@1 {
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+ compatible = "ethernet-phy-ieee802.3-c22";
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+ reg = <1>;
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+ };
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+};
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+
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+&mmc0 {
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+ broken-cd;
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+ bus-width = <4>;
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+ disable-wp;
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+ vmmc-supply = <®_vcc_3v3>;
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+ vqmmc-supply = <®_vcc_3v3>;
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+ pinctrl-0 = <&mmc0_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&ohci0 {
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+ status = "okay";
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+};
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+
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+&uart0 {
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+ pinctrl-0 = <&uart0_pb8_pins>;
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+ pinctrl-names = "default";
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+ status = "okay";
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+};
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+
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+&usb_otg {
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+ dr_mode = "otg";
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+ status = "okay";
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+};
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+
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+&usbphy {
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+ usb0_id_det-gpios = <&pio 3 21 GPIO_ACTIVE_HIGH>; /* PD21 */
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+ usb0_vbus_det-gpios = <&pio 3 20 GPIO_ACTIVE_HIGH>; /* PD20 */
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+ usb0_vbus-supply = <®_usbvbus>;
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+ status = "okay";
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+};
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