mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
8a9273d51e
Copy backport, hack, pending patch and config from 6.1 to 6.6. Signed-off-by: Weijie Gao <hackpascal@gmail.com>
82 lines
2.3 KiB
Diff
82 lines
2.3 KiB
Diff
From 7d88d79c0f65b27a92754d7547f7af098b3de67b Mon Sep 17 00:00:00 2001
|
|
From: Daniel Golle <daniel@makrotopia.org>
|
|
Date: Tue, 12 Dec 2023 03:47:31 +0000
|
|
Subject: [PATCH 4/5] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
|
|
PCS
|
|
|
|
MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
|
|
it in order to configure and monitor the Ethernet SerDes link in
|
|
USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
|
|
legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
|
|
interface modes are also available.
|
|
|
|
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
|
|
---
|
|
.../bindings/net/pcs/mediatek,usxgmii.yaml | 60 +++++++++++++++++++
|
|
1 file changed, 60 insertions(+)
|
|
create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
|
|
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
|
|
@@ -0,0 +1,60 @@
|
|
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
+%YAML 1.2
|
|
+---
|
|
+$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
|
|
+$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
+
|
|
+title: MediaTek USXGMII PCS
|
|
+
|
|
+maintainers:
|
|
+ - Daniel Golle <daniel@makrotopia.org>
|
|
+
|
|
+description:
|
|
+ The MediaTek USXGMII PCS provides physical link control and status
|
|
+ for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
|
|
+ provided by the PEXTP PHY.
|
|
+ In order to also support legacy 2500Base-X, 1000Base-X and Cisco
|
|
+ SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
|
|
+ provide those interfaces modes on the same SerDes interfaces shared
|
|
+ with the USXGMII PCS.
|
|
+
|
|
+properties:
|
|
+ $nodename:
|
|
+ pattern: "^pcs@[0-9a-f]+$"
|
|
+
|
|
+ compatible:
|
|
+ const: mediatek,mt7988-usxgmiisys
|
|
+
|
|
+ reg:
|
|
+ maxItems: 1
|
|
+
|
|
+ clocks:
|
|
+ items:
|
|
+ - description: USXGMII top-level clock
|
|
+
|
|
+ resets:
|
|
+ items:
|
|
+ - description: XFI reset
|
|
+
|
|
+required:
|
|
+ - compatible
|
|
+ - reg
|
|
+ - clocks
|
|
+ - resets
|
|
+
|
|
+additionalProperties: false
|
|
+
|
|
+examples:
|
|
+ - |
|
|
+ #include <dt-bindings/clock/mediatek,mt7988-clk.h>
|
|
+ #define MT7988_TOPRGU_XFI0_GRST 12
|
|
+ soc {
|
|
+ #address-cells = <2>;
|
|
+ #size-cells = <2>;
|
|
+ usxgmiisys0: pcs@10080000 {
|
|
+ compatible = "mediatek,mt7988-usxgmiisys";
|
|
+ reg = <0 0x10080000 0 0x1000>;
|
|
+ clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
|
|
+ resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
|
|
+ };
|
|
+ };
|