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0dcbe4e931
Copy config and patches from 5.15. This simplifies reviewing process. Signed-off-by: Nick Hainke <vincent@systemli.org>
103 lines
2.9 KiB
Diff
103 lines
2.9 KiB
Diff
From ad38c17b0c26ae2108b50ac1eb0281a2e1ce08e9 Mon Sep 17 00:00:00 2001
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From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Date: Mon, 19 Jun 2023 06:09:40 +0200
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Subject: [PATCH 8/9] mips: ralink: get cpu rate from new driver code
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At very early stage on boot, there is a need to set 'mips_hpt_frequency'.
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This timer frequency is a half of the CPU frequency. To get clocks properly
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set we need to call to 'of_clk_init()' and properly get cpu clock frequency
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afterwards. Depending on the SoC, CPU clock index and compatible differs, so
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use them to get the proper clock frm the clock provider. Hence, adapt code
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to be aligned with new clock driver.
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Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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arch/mips/ralink/clk.c | 61 ++++++++++++++++++++++++++++++++++++++++++--------
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1 file changed, 52 insertions(+), 9 deletions(-)
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--- a/arch/mips/ralink/clk.c
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+++ b/arch/mips/ralink/clk.c
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@@ -11,29 +11,72 @@
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#include <linux/clkdev.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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+#include <asm/mach-ralink/ralink_regs.h>
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#include <asm/time.h>
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#include "common.h"
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-void ralink_clk_add(const char *dev, unsigned long rate)
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+static const char *clk_cpu(int *idx)
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{
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- struct clk *clk = clk_register_fixed_rate(NULL, dev, NULL, 0, rate);
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-
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- if (!clk)
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- panic("failed to add clock");
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-
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- clkdev_create(clk, NULL, "%s", dev);
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+ switch (ralink_soc) {
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+ case RT2880_SOC:
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+ *idx = 0;
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+ return "ralink,rt2880-sysc";
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+ case RT3883_SOC:
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+ *idx = 0;
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+ return "ralink,rt3883-sysc";
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+ case RT305X_SOC_RT3050:
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+ *idx = 0;
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+ return "ralink,rt3050-sysc";
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+ case RT305X_SOC_RT3052:
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+ *idx = 0;
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+ return "ralink,rt3052-sysc";
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+ case RT305X_SOC_RT3350:
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+ *idx = 1;
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+ return "ralink,rt3350-sysc";
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+ case RT305X_SOC_RT3352:
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+ *idx = 1;
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+ return "ralink,rt3352-sysc";
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+ case RT305X_SOC_RT5350:
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+ *idx = 1;
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+ return "ralink,rt5350-sysc";
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+ case MT762X_SOC_MT7620A:
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+ *idx = 2;
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+ return "ralink,mt7620-sysc";
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+ case MT762X_SOC_MT7620N:
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+ *idx = 2;
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+ return "ralink,mt7620-sysc";
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+ case MT762X_SOC_MT7628AN:
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+ *idx = 1;
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+ return "ralink,mt7628-sysc";
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+ case MT762X_SOC_MT7688:
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+ *idx = 1;
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+ return "ralink,mt7688-sysc";
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+ default:
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+ *idx = -1;
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+ return "invalid";
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+ }
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}
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void __init plat_time_init(void)
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{
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+ struct of_phandle_args clkspec;
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+ const char *compatible;
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struct clk *clk;
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+ int cpu_clk_idx;
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ralink_of_remap();
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- ralink_clk_init();
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- clk = clk_get_sys("cpu", NULL);
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+ compatible = clk_cpu(&cpu_clk_idx);
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+ if (cpu_clk_idx == -1)
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+ panic("unable to get CPU clock index");
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+
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+ of_clk_init(NULL);
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+ clkspec.np = of_find_compatible_node(NULL, NULL, compatible);
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+ clkspec.args_count = 1;
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+ clkspec.args[0] = cpu_clk_idx;
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+ clk = of_clk_get_from_provider(&clkspec);
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if (IS_ERR(clk))
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panic("unable to get CPU clock, err=%ld", PTR_ERR(clk));
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pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000);
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