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1f818b09f8
This series of upstream patches properly implement a clock and reset driver for old ralink SoCs[1]. And it includes some related fixes[2] and improvements[3][4]. All patches have been merged into linux-next. They will be part of upcoming Linux 6.5. In order to switch to the new system controller driver, all clocks and resets properties in SoC dtsi have been updated, and kernel symbol "CONFIG_CLK_MTMIPS" have been added to the kernel config files. [1] https://lore.kernel.org/all/20230619040941.1340372-1-sergio.paracuellos@gmail.com [2] https://lore.kernel.org/all/20230622-mips-ralink-clk-wuninitialized-v1-1-ea9041240d10@kernel.org [3] https://lore.kernel.org/all/OSYP286MB03120BABB25900E113ED42B7BC5CA@OSYP286MB0312.JPNP286.PROD.OUTLOOK.COM [4] https://lore.kernel.org/all/TYAP286MB03151148AF8C054621DD55C3BC23A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM Tested on Motorola MWR03 (MT7628) Tested on Haier HW-L1W (MT7620) Signed-off-by: Shiji Yang <yangshiji66@qq.com>
20 lines
506 B
Diff
20 lines
506 B
Diff
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
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+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
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@@ -61,4 +61,16 @@ static inline int mt7620_get_eco(void)
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return rt_sysc_r32(SYSC_REG_CHIP_REV) & CHIP_REV_ECO_MASK;
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}
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+static inline int mt7620_get_chipver(void)
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+{
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+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_VER_SHIFT) &
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+ CHIP_REV_VER_MASK;
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+}
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+
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+static inline int mt7620_get_pkg(void)
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+{
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+ return (rt_sysc_r32(SYSC_REG_CHIP_REV) >> CHIP_REV_PKG_SHIFT) &
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+ CHIP_REV_PKG_MASK;
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+}
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+
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#endif
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