openwrt/target/linux/ramips/dts/mt7620a_linksys_e1700.dts

// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (C) 2014 Imre Kaloz <kaloz@openwrt.org>
 */

#include "mt7620a.dtsi"

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>

/ {
	compatible = "linksys,e1700", "ralink,mt7620a-soc";
	model = "Linksys E1700";

	aliases {
		led-boot = &led_power;
		led-failsafe = &led_power;
		led-running = &led_power;
		led-upgrade = &led_power;
	};

	keys {
		compatible = "gpio-keys";

		reset {
			label = "reset";
			gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_RESTART>;
		};

		wps {
			label = "wps";
			gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
			linux,code = <KEY_WPS_BUTTON>;
		};
	};

	leds {
		compatible = "gpio-leds";

		led_power: power {
			function = LED_FUNCTION_POWER;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 10 GPIO_ACTIVE_LOW>;
		};

		wan {
			function = LED_FUNCTION_WPS;
			color = <LED_COLOR_ID_GREEN>;
			gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
		};
	};
};

&spi0 {
	status = "okay";

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "u-boot";
				reg = <0x0 0x30000>;
				read-only;
			};

			partition@30000 {
				label = "config";
				reg = <0x30000 0x10000>;
				read-only;
			};

			factory: partition@40000 {
				label = "factory";
				reg = <0x40000 0x10000>;
				read-only;

				nvmem-layout {
					compatible = "fixed-layout";
					#address-cells = <1>;
					#size-cells = <1>;

					eeprom_factory_0: eeprom@0 {
						reg = <0x0 0x200>;
					};

					macaddr_factory_28: macaddr@28 {
						reg = <0x28 0x6>;
					};
				};
			};

			partition@50000 {
				compatible = "denx,uimage";
				label = "firmware";
				reg = <0x50000 0x7b0000>;
			};
		};
	};
};

&state_default {
	gpio {
		groups = "i2c", "uartf";
		function = "gpio";
	};
};

&ethernet {
	pinctrl-names = "default";
	pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;

	nvmem-cells = <&macaddr_factory_28>;
	nvmem-cell-names = "mac-address";

	port@5 {
		status = "okay";
		mediatek,fixed-link = <1000 1 1 1>;
		phy-mode = "rgmii";
	};

	mdio-bus {
		status = "okay";

		phy0: ethernet-phy@0 {
			reg = <0>;
			phy-mode = "rgmii";
		};

		phy1: ethernet-phy@1 {
			reg = <1>;
			phy-mode = "rgmii";
		};

		phy2: ethernet-phy@2 {
			reg = <2>;
			phy-mode = "rgmii";
		};

		phy3: ethernet-phy@3 {
			reg = <3>;
			phy-mode = "rgmii";
		};

		phy4: ethernet-phy@4 {
			reg = <4>;
			phy-mode = "rgmii";
		};

		phy1f: ethernet-phy@1f {
			reg = <0x1f>;
			phy-mode = "rgmii";
		};
	};
};

&gsw {
	mediatek,ephy-base = /bits/ 8 <12>;
};

&wmac {
	nvmem-cells = <&eeprom_factory_0>;
	nvmem-cell-names = "eeprom";
};