mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-30 18:47:06 +00:00
fa79baf4a6
Copy backport, hack, pending patch and config from 5.15 to 6.1. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
346 lines
11 KiB
Diff
346 lines
11 KiB
Diff
From patchwork Wed Mar 22 17:15:15 2023
|
|
Content-Type: text/plain; charset="utf-8"
|
|
MIME-Version: 1.0
|
|
Content-Transfer-Encoding: 8bit
|
|
X-Patchwork-Submitter: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?=
|
|
<noltari@gmail.com>
|
|
X-Patchwork-Id: 13184392
|
|
Return-Path: <linux-clk-owner@vger.kernel.org>
|
|
X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on
|
|
aws-us-west-2-korg-lkml-1.web.codeaurora.org
|
|
Received: from vger.kernel.org (vger.kernel.org [23.128.96.18])
|
|
by smtp.lore.kernel.org (Postfix) with ESMTP id 199D9C76196
|
|
for <linux-clk@archiver.kernel.org>; Wed, 22 Mar 2023 17:16:11 +0000 (UTC)
|
|
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
|
|
id S231512AbjCVRQJ (ORCPT <rfc822;linux-clk@archiver.kernel.org>);
|
|
Wed, 22 Mar 2023 13:16:09 -0400
|
|
Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58942 "EHLO
|
|
lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
|
|
with ESMTP id S231442AbjCVRP5 (ORCPT
|
|
<rfc822;linux-clk@vger.kernel.org>); Wed, 22 Mar 2023 13:15:57 -0400
|
|
Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com
|
|
[IPv6:2a00:1450:4864:20::32c])
|
|
by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DDB36487D;
|
|
Wed, 22 Mar 2023 10:15:27 -0700 (PDT)
|
|
Received: by mail-wm1-x32c.google.com with SMTP id
|
|
i5-20020a05600c354500b003edd24054e0so6717370wmq.4;
|
|
Wed, 22 Mar 2023 10:15:27 -0700 (PDT)
|
|
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
|
|
d=gmail.com; s=20210112; t=1679505325;
|
|
h=content-transfer-encoding:mime-version:references:in-reply-to
|
|
:message-id:date:subject:cc:to:from:from:to:cc:subject:date
|
|
:message-id:reply-to;
|
|
bh=rkv/eZYA1ncHp5FnV2ZWc3hgYnAx28S86QA9vmcXFCY=;
|
|
b=Y1mva2Bt3sUbKxLgEUS331CJbGxUc4z8kTQW8qiHWGhYlFKtm+d5z4sT40E5BeZAnU
|
|
zmTbCI7jbroe9NYBxGUmSli6LNVDPjND80ChbhWTqbqMQTmeQFWut9KmeBWK6Oze2lC/
|
|
XMSOorUzowjcU2xtHNrzoq2KH2pstW573lsB8WnzFVfhMaRkE9DfRr6WNyA7zC8DyxM5
|
|
ezxlCQtCmgPfCqlyksbIDKrgrRf3GiUR0yUd6xRU+MssyvH1FkYGDCerPctDto6lGHBz
|
|
8Y15jT3l6OnQMT6dkekgpPF5/XrSUY93u9g0B4U8+0dhNj+K7vmDen+jqdess+tpLnq/
|
|
gFrA==
|
|
X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed;
|
|
d=1e100.net; s=20210112; t=1679505325;
|
|
h=content-transfer-encoding:mime-version:references:in-reply-to
|
|
:message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc
|
|
:subject:date:message-id:reply-to;
|
|
bh=rkv/eZYA1ncHp5FnV2ZWc3hgYnAx28S86QA9vmcXFCY=;
|
|
b=Ym4+u8bbTQGNkewUBrLf+89vE0EFJBQp2f1crwUxZFboKTROF9ltZonY1CGepo7b0B
|
|
fkx3TbWQy5X65g3ScuieqtClCI8WanPeNBJ48+JipJYO3ODVNBxnVaTuW/0FOIcahfqe
|
|
sG5GvggHhzRz+Yeybsbnupmzxnw8Ez0BpMl3p7zcjHL7BGZDdOOX2Zbw3zfyYa5sg2nX
|
|
UXYJT36zy2h39gxUsy9QkhQ76CG3w6omniohZpYidpojpiDjbOy0nKFky4kUe+YyA1fF
|
|
4IBhjAm6mH+uh6wHSG1qj+NAXHs0xDDJps16PbJwAgL7Qt9K5WW+R/UAYPmHFgaRIHOw
|
|
/seA==
|
|
X-Gm-Message-State: AO0yUKXRtoYO8Nfus6Ca8lhM39P1Xn6TGkhatEfoISd1YNOkTJJN2hW+
|
|
xRphLgxlzNfCLcVPlpGK9dk=
|
|
X-Google-Smtp-Source:
|
|
AK7set9VnMEykugk8ZYnkXuqK41bX1dzlvKsAXHEjr8i2NZBld0buKhQLcGYEcwxnBgVTtC7eRGfXw==
|
|
X-Received: by 2002:a1c:7c0b:0:b0:3e2:1dac:b071 with SMTP id
|
|
x11-20020a1c7c0b000000b003e21dacb071mr178053wmc.13.1679505325582;
|
|
Wed, 22 Mar 2023 10:15:25 -0700 (PDT)
|
|
Received: from atlantis.lan (255.red-79-146-124.dynamicip.rima-tde.net.
|
|
[79.146.124.255])
|
|
by smtp.gmail.com with ESMTPSA id
|
|
v10-20020a05600c470a00b003ee11ac2288sm8414333wmo.21.2023.03.22.10.15.24
|
|
(version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);
|
|
Wed, 22 Mar 2023 10:15:25 -0700 (PDT)
|
|
From: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= <noltari@gmail.com>
|
|
To: mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org,
|
|
krzysztof.kozlowski+dt@linaro.org, p.zabel@pengutronix.de,
|
|
f.fainelli@gmail.com, jonas.gorski@gmail.com,
|
|
william.zhang@broadcom.com, linux-clk@vger.kernel.org,
|
|
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
|
|
Cc: =?utf-8?q?=C3=81lvaro_Fern=C3=A1ndez_Rojas?= <noltari@gmail.com>
|
|
Subject: [PATCH v4 4/4] clk: bcm: Add BCM63268 timer clock and reset driver
|
|
Date: Wed, 22 Mar 2023 18:15:15 +0100
|
|
Message-Id: <20230322171515.120353-5-noltari@gmail.com>
|
|
X-Mailer: git-send-email 2.30.2
|
|
In-Reply-To: <20230322171515.120353-1-noltari@gmail.com>
|
|
References: <20230322171515.120353-1-noltari@gmail.com>
|
|
MIME-Version: 1.0
|
|
Precedence: bulk
|
|
List-ID: <linux-clk.vger.kernel.org>
|
|
X-Mailing-List: linux-clk@vger.kernel.org
|
|
|
|
Add driver for BCM63268 timer clock and reset controller.
|
|
|
|
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
|
|
---
|
|
v4: add changes suggested by Stephen Boyd:
|
|
- Usage of of_device_get_match_data() isn't needed.
|
|
- Use devm_clk_hw_register_gate().
|
|
- Drop clk_hw_unregister_gate().
|
|
v3: add missing <linux/io.h> include to fix build warning
|
|
v2: add changes suggested by Stephen Boyd
|
|
|
|
drivers/clk/bcm/Kconfig | 9 ++
|
|
drivers/clk/bcm/Makefile | 1 +
|
|
drivers/clk/bcm/clk-bcm63268-timer.c | 215 +++++++++++++++++++++++++++
|
|
3 files changed, 225 insertions(+)
|
|
create mode 100644 drivers/clk/bcm/clk-bcm63268-timer.c
|
|
|
|
--- a/drivers/clk/bcm/Kconfig
|
|
+++ b/drivers/clk/bcm/Kconfig
|
|
@@ -37,6 +37,15 @@ config CLK_BCM_63XX_GATE
|
|
Enable common clock framework support for Broadcom BCM63xx DSL SoCs
|
|
based on the MIPS architecture
|
|
|
|
+config CLK_BCM63268_TIMER
|
|
+ bool "Broadcom BCM63268 timer clock and reset support"
|
|
+ depends on BMIPS_GENERIC || COMPILE_TEST
|
|
+ default BMIPS_GENERIC
|
|
+ select RESET_CONTROLLER
|
|
+ help
|
|
+ Enable timer clock and reset support for Broadcom BCM63268 DSL SoCs
|
|
+ based on the MIPS architecture.
|
|
+
|
|
config CLK_BCM_KONA
|
|
bool "Broadcom Kona CCU clock support"
|
|
depends on ARCH_BCM_MOBILE || COMPILE_TEST
|
|
--- a/drivers/clk/bcm/Makefile
|
|
+++ b/drivers/clk/bcm/Makefile
|
|
@@ -1,6 +1,7 @@
|
|
# SPDX-License-Identifier: GPL-2.0
|
|
obj-$(CONFIG_CLK_BCM_63XX) += clk-bcm63xx.o
|
|
obj-$(CONFIG_CLK_BCM_63XX_GATE) += clk-bcm63xx-gate.o
|
|
+obj-$(CONFIG_CLK_BCM63268_TIMER) += clk-bcm63268-timer.o
|
|
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona.o
|
|
obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
|
|
obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
|
|
--- /dev/null
|
|
+++ b/drivers/clk/bcm/clk-bcm63268-timer.c
|
|
@@ -0,0 +1,215 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * BCM63268 Timer Clock and Reset Controller Driver
|
|
+ *
|
|
+ * Copyright (C) 2023 Álvaro Fernández Rojas <noltari@gmail.com>
|
|
+ */
|
|
+
|
|
+#include <linux/clk-provider.h>
|
|
+#include <linux/delay.h>
|
|
+#include <linux/io.h>
|
|
+#include <linux/of.h>
|
|
+#include <linux/of_device.h>
|
|
+#include <linux/platform_device.h>
|
|
+#include <linux/reset-controller.h>
|
|
+
|
|
+#include <dt-bindings/clock/bcm63268-clock.h>
|
|
+
|
|
+#define BCM63268_TIMER_RESET_SLEEP_MIN_US 10000
|
|
+#define BCM63268_TIMER_RESET_SLEEP_MAX_US 20000
|
|
+
|
|
+struct bcm63268_tclkrst_hw {
|
|
+ void __iomem *regs;
|
|
+ spinlock_t lock;
|
|
+
|
|
+ struct reset_controller_dev rcdev;
|
|
+ struct clk_hw_onecell_data data;
|
|
+};
|
|
+
|
|
+struct bcm63268_tclk_table_entry {
|
|
+ const char * const name;
|
|
+ u8 bit;
|
|
+};
|
|
+
|
|
+static const struct bcm63268_tclk_table_entry bcm63268_timer_clocks[] = {
|
|
+ {
|
|
+ .name = "ephy1",
|
|
+ .bit = BCM63268_TCLK_EPHY1,
|
|
+ }, {
|
|
+ .name = "ephy2",
|
|
+ .bit = BCM63268_TCLK_EPHY2,
|
|
+ }, {
|
|
+ .name = "ephy3",
|
|
+ .bit = BCM63268_TCLK_EPHY3,
|
|
+ }, {
|
|
+ .name = "gphy1",
|
|
+ .bit = BCM63268_TCLK_GPHY1,
|
|
+ }, {
|
|
+ .name = "dsl",
|
|
+ .bit = BCM63268_TCLK_DSL,
|
|
+ }, {
|
|
+ .name = "wakeon_ephy",
|
|
+ .bit = BCM63268_TCLK_WAKEON_EPHY,
|
|
+ }, {
|
|
+ .name = "wakeon_dsl",
|
|
+ .bit = BCM63268_TCLK_WAKEON_DSL,
|
|
+ }, {
|
|
+ .name = "fap1_pll",
|
|
+ .bit = BCM63268_TCLK_FAP1,
|
|
+ }, {
|
|
+ .name = "fap2_pll",
|
|
+ .bit = BCM63268_TCLK_FAP2,
|
|
+ }, {
|
|
+ .name = "uto_50",
|
|
+ .bit = BCM63268_TCLK_UTO_50,
|
|
+ }, {
|
|
+ .name = "uto_extin",
|
|
+ .bit = BCM63268_TCLK_UTO_EXTIN,
|
|
+ }, {
|
|
+ .name = "usb_ref",
|
|
+ .bit = BCM63268_TCLK_USB_REF,
|
|
+ }, {
|
|
+ /* sentinel */
|
|
+ }
|
|
+};
|
|
+
|
|
+static inline struct bcm63268_tclkrst_hw *
|
|
+to_bcm63268_timer_reset(struct reset_controller_dev *rcdev)
|
|
+{
|
|
+ return container_of(rcdev, struct bcm63268_tclkrst_hw, rcdev);
|
|
+}
|
|
+
|
|
+static int bcm63268_timer_reset_update(struct reset_controller_dev *rcdev,
|
|
+ unsigned long id, bool assert)
|
|
+{
|
|
+ struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
|
|
+ unsigned long flags;
|
|
+ uint32_t val;
|
|
+
|
|
+ spin_lock_irqsave(&reset->lock, flags);
|
|
+ val = __raw_readl(reset->regs);
|
|
+ if (assert)
|
|
+ val &= ~BIT(id);
|
|
+ else
|
|
+ val |= BIT(id);
|
|
+ __raw_writel(val, reset->regs);
|
|
+ spin_unlock_irqrestore(&reset->lock, flags);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63268_timer_reset_assert(struct reset_controller_dev *rcdev,
|
|
+ unsigned long id)
|
|
+{
|
|
+ return bcm63268_timer_reset_update(rcdev, id, true);
|
|
+}
|
|
+
|
|
+static int bcm63268_timer_reset_deassert(struct reset_controller_dev *rcdev,
|
|
+ unsigned long id)
|
|
+{
|
|
+ return bcm63268_timer_reset_update(rcdev, id, false);
|
|
+}
|
|
+
|
|
+static int bcm63268_timer_reset_reset(struct reset_controller_dev *rcdev,
|
|
+ unsigned long id)
|
|
+{
|
|
+ bcm63268_timer_reset_update(rcdev, id, true);
|
|
+ usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
|
|
+ BCM63268_TIMER_RESET_SLEEP_MAX_US);
|
|
+
|
|
+ bcm63268_timer_reset_update(rcdev, id, false);
|
|
+ /*
|
|
+ * Ensure component is taken out reset state by sleeping also after
|
|
+ * deasserting the reset. Otherwise, the component may not be ready
|
|
+ * for operation.
|
|
+ */
|
|
+ usleep_range(BCM63268_TIMER_RESET_SLEEP_MIN_US,
|
|
+ BCM63268_TIMER_RESET_SLEEP_MAX_US);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm63268_timer_reset_status(struct reset_controller_dev *rcdev,
|
|
+ unsigned long id)
|
|
+{
|
|
+ struct bcm63268_tclkrst_hw *reset = to_bcm63268_timer_reset(rcdev);
|
|
+
|
|
+ return !(__raw_readl(reset->regs) & BIT(id));
|
|
+}
|
|
+
|
|
+static struct reset_control_ops bcm63268_timer_reset_ops = {
|
|
+ .assert = bcm63268_timer_reset_assert,
|
|
+ .deassert = bcm63268_timer_reset_deassert,
|
|
+ .reset = bcm63268_timer_reset_reset,
|
|
+ .status = bcm63268_timer_reset_status,
|
|
+};
|
|
+
|
|
+static int bcm63268_tclk_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct device *dev = &pdev->dev;
|
|
+ const struct bcm63268_tclk_table_entry *entry;
|
|
+ struct bcm63268_tclkrst_hw *hw;
|
|
+ struct clk_hw *clk;
|
|
+ u8 maxbit = 0;
|
|
+ int i, ret;
|
|
+
|
|
+ for (entry = bcm63268_timer_clocks; entry->name; entry++)
|
|
+ maxbit = max(maxbit, entry->bit);
|
|
+ maxbit++;
|
|
+
|
|
+ hw = devm_kzalloc(&pdev->dev, struct_size(hw, data.hws, maxbit),
|
|
+ GFP_KERNEL);
|
|
+ if (!hw)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ platform_set_drvdata(pdev, hw);
|
|
+
|
|
+ spin_lock_init(&hw->lock);
|
|
+
|
|
+ hw->data.num = maxbit;
|
|
+ for (i = 0; i < maxbit; i++)
|
|
+ hw->data.hws[i] = ERR_PTR(-ENODEV);
|
|
+
|
|
+ hw->regs = devm_platform_ioremap_resource(pdev, 0);
|
|
+ if (IS_ERR(hw->regs))
|
|
+ return PTR_ERR(hw->regs);
|
|
+
|
|
+ for (entry = bcm63268_timer_clocks; entry->name; entry++) {
|
|
+ clk = devm_clk_hw_register_gate(dev, entry->name, NULL, 0,
|
|
+ hw->regs, entry->bit,
|
|
+ CLK_GATE_BIG_ENDIAN,
|
|
+ &hw->lock);
|
|
+ if (IS_ERR(clk))
|
|
+ return PTR_ERR(clk);
|
|
+
|
|
+ hw->data.hws[entry->bit] = clk;
|
|
+ }
|
|
+
|
|
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
|
|
+ &hw->data);
|
|
+ if (ret)
|
|
+ return ret;
|
|
+
|
|
+ hw->rcdev.of_node = dev->of_node;
|
|
+ hw->rcdev.ops = &bcm63268_timer_reset_ops;
|
|
+
|
|
+ ret = devm_reset_controller_register(dev, &hw->rcdev);
|
|
+ if (ret)
|
|
+ dev_err(dev, "Failed to register reset controller\n");
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id bcm63268_tclk_dt_ids[] = {
|
|
+ { .compatible = "brcm,bcm63268-timer-clocks" },
|
|
+ { /* sentinel */ }
|
|
+};
|
|
+
|
|
+static struct platform_driver bcm63268_tclk = {
|
|
+ .probe = bcm63268_tclk_probe,
|
|
+ .driver = {
|
|
+ .name = "bcm63268-timer-clock",
|
|
+ .of_match_table = bcm63268_tclk_dt_ids,
|
|
+ },
|
|
+};
|
|
+builtin_platform_driver(bcm63268_tclk);
|