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7deb73e6ed
It seems that I forgot one zero in the patch numbering while marking these as backports, so lets fix it. Signed-off-by: Robert Marko <robimarko@gmail.com>
44 lines
1.3 KiB
Diff
44 lines
1.3 KiB
Diff
From c917237a7cb17b97cc48e073881a9873f3caeaa2 Mon Sep 17 00:00:00 2001
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From: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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Date: Thu, 14 Sep 2023 12:29:57 +0530
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Subject: [PATCH] clk: qcom: apss-ipq6018: add the GPLL0 clock also as clock
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provider
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While the kernel is booting up, APSS PLL will be running at 800MHz with
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GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be
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configured and select the rate based on the opp table and the source will
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be changed to APSS_PLL_EARLY.
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Without this patch, CPU Freq driver reports that CPU is running at 24MHz
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instead of the 800MHz.
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Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
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Tested-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com>
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---
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drivers/clk/qcom/apss-ipq6018.c | 3 +++
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1 file changed, 3 insertions(+)
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--- a/drivers/clk/qcom/apss-ipq6018.c
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+++ b/drivers/clk/qcom/apss-ipq6018.c
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@@ -20,16 +20,19 @@
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enum {
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P_XO,
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+ P_GPLL0,
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P_APSS_PLL_EARLY,
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};
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static const struct clk_parent_data parents_apcs_alias0_clk_src[] = {
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{ .fw_name = "xo" },
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+ { .fw_name = "gpll0" },
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{ .fw_name = "pll" },
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};
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static const struct parent_map parents_apcs_alias0_clk_src_map[] = {
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{ P_XO, 0 },
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+ { P_GPLL0, 4 },
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{ P_APSS_PLL_EARLY, 5 },
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};
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