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125 lines
3.9 KiB
Diff
125 lines
3.9 KiB
Diff
From 317c5224795b41a08ba8c08573d74ba95096faa5 Mon Sep 17 00:00:00 2001
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From: Reinder de Haan <patchesrdh@mveas.com>
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Date: Fri, 11 Dec 2015 16:32:18 +0100
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Subject: [PATCH] phy-sun4i-usb: Add support for the host usb-phys found on the
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H3 SoC
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Note this commit only adds support for phys 1-3, phy 0, the otg phy, is
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not yet (fully) supported after this commit.
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Signed-off-by: Reinder de Haan <patchesrdh@mveas.com>
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Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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Acked-by: Rob Herring <robh@kernel.org>
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Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
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---
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.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
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drivers/phy/phy-sun4i-usb.c | 41 +++++++++++++++++-----
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2 files changed, 33 insertions(+), 9 deletions(-)
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--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
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+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
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@@ -9,6 +9,7 @@ Required properties:
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* allwinner,sun7i-a20-usb-phy
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* allwinner,sun8i-a23-usb-phy
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* allwinner,sun8i-a33-usb-phy
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+ * allwinner,sun8i-h3-usb-phy
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- reg : a list of offset + length pairs
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- reg-names :
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* "phy_ctrl"
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--- a/drivers/phy/phy-sun4i-usb.c
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+++ b/drivers/phy/phy-sun4i-usb.c
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@@ -47,6 +47,9 @@
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#define REG_PHYBIST 0x08
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#define REG_PHYTUNE 0x0c
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#define REG_PHYCTL_A33 0x10
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+#define REG_PHY_UNK_H3 0x20
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+
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+#define REG_PMU_UNK_H3 0x10
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#define PHYCTL_DATA BIT(7)
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@@ -80,7 +83,7 @@
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#define PHY_DISCON_TH_SEL 0x2a
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#define PHY_SQUELCH_DETECT 0x3c
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-#define MAX_PHYS 3
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+#define MAX_PHYS 4
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/*
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* Note do not raise the debounce time, we must report Vusb high within 100ms
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@@ -92,6 +95,7 @@
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enum sun4i_usb_phy_type {
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sun4i_a10_phy,
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sun8i_a33_phy,
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+ sun8i_h3_phy,
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};
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struct sun4i_usb_phy_cfg {
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@@ -239,6 +243,7 @@ static int sun4i_usb_phy_init(struct phy
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struct sun4i_usb_phy *phy = phy_get_drvdata(_phy);
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struct sun4i_usb_phy_data *data = to_sun4i_usb_phy_data(phy);
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int ret;
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+ u32 val;
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ret = clk_prepare_enable(phy->clk);
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if (ret)
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@@ -250,16 +255,26 @@ static int sun4i_usb_phy_init(struct phy
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return ret;
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}
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- /* Enable USB 45 Ohm resistor calibration */
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- if (phy->index == 0)
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- sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
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-
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- /* Adjust PHY's magnitude and rate */
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- sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
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-
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- /* Disconnect threshold adjustment */
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- sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
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- data->cfg->disc_thresh, 2);
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+ if (data->cfg->type == sun8i_h3_phy) {
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+ if (phy->index == 0) {
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+ val = readl(data->base + REG_PHY_UNK_H3);
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+ writel(val & ~1, data->base + REG_PHY_UNK_H3);
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+ }
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+
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+ val = readl(phy->pmu + REG_PMU_UNK_H3);
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+ writel(val & ~2, phy->pmu + REG_PMU_UNK_H3);
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+ } else {
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+ /* Enable USB 45 Ohm resistor calibration */
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+ if (phy->index == 0)
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+ sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN, 0x01, 1);
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+
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+ /* Adjust PHY's magnitude and rate */
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+ sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE, 0x14, 5);
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+
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+ /* Disconnect threshold adjustment */
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+ sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
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+ data->cfg->disc_thresh, 2);
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+ }
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sun4i_usb_phy_passby(phy, 1);
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@@ -726,6 +741,13 @@ static const struct sun4i_usb_phy_cfg su
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.dedicated_clocks = true,
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};
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+static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
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+ .num_phys = 4,
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+ .type = sun8i_h3_phy,
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+ .disc_thresh = 3,
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+ .dedicated_clocks = true,
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+};
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+
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static const struct of_device_id sun4i_usb_phy_of_match[] = {
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{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
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{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
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@@ -733,6 +755,7 @@ static const struct of_device_id sun4i_u
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{ .compatible = "allwinner,sun7i-a20-usb-phy", .data = &sun7i_a20_cfg },
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{ .compatible = "allwinner,sun8i-a23-usb-phy", .data = &sun8i_a23_cfg },
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{ .compatible = "allwinner,sun8i-a33-usb-phy", .data = &sun8i_a33_cfg },
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+ { .compatible = "allwinner,sun8i-h3-usb-phy", .data = &sun8i_h3_cfg },
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{ },
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};
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MODULE_DEVICE_TABLE(of, sun4i_usb_phy_of_match);
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