mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
8c405cdccc
The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
60 lines
1.7 KiB
Diff
60 lines
1.7 KiB
Diff
From 7f7a5d80c4eb0207713ef938737f56fdebcd1cb3 Mon Sep 17 00:00:00 2001
|
|
From: Dave Stevenson <dave.stevenson@raspberrypi.com>
|
|
Date: Wed, 8 Jun 2022 17:23:47 +0100
|
|
Subject: [PATCH 1062/1085] drm: vc4: dsi: Clocks should be running before
|
|
reset
|
|
|
|
The initialisation sequence differs slightly from the documentation
|
|
in that the clocks are meant to be running before resets and
|
|
similar.
|
|
|
|
Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_dsi.c | 28 ++++++++++++++--------------
|
|
1 file changed, 14 insertions(+), 14 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_dsi.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_dsi.c
|
|
@@ -926,6 +926,20 @@ static void vc4_dsi_bridge_pre_enable(st
|
|
"Failed to set phy clock to %ld: %d\n", phy_clock, ret);
|
|
}
|
|
|
|
+ ret = clk_prepare_enable(dsi->escape_clock);
|
|
+ if (ret) {
|
|
+ DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ ret = clk_prepare_enable(dsi->pll_phy_clock);
|
|
+ if (ret) {
|
|
+ DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
|
|
+ return;
|
|
+ }
|
|
+
|
|
+ hs_clock = clk_get_rate(dsi->pll_phy_clock);
|
|
+
|
|
/* Reset the DSI and all its fifos. */
|
|
DSI_PORT_WRITE(CTRL,
|
|
DSI_CTRL_SOFT_RESET_CFG |
|
|
@@ -984,20 +998,6 @@ static void vc4_dsi_bridge_pre_enable(st
|
|
mdelay(1);
|
|
}
|
|
|
|
- ret = clk_prepare_enable(dsi->escape_clock);
|
|
- if (ret) {
|
|
- DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret);
|
|
- return;
|
|
- }
|
|
-
|
|
- ret = clk_prepare_enable(dsi->pll_phy_clock);
|
|
- if (ret) {
|
|
- DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret);
|
|
- return;
|
|
- }
|
|
-
|
|
- hs_clock = clk_get_rate(dsi->pll_phy_clock);
|
|
-
|
|
/* Yes, we set the DSI0P/DSI1P pixel clock to the byte rate,
|
|
* not the pixel clock rate. DSIxP take from the APHY's byte,
|
|
* DDR2, or DDR4 clock (we use byte) and feed into the PV at
|