mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
205 lines
7.8 KiB
Diff
205 lines
7.8 KiB
Diff
--- a/drivers/ssb/b43_pci_bridge.c
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+++ b/drivers/ssb/b43_pci_bridge.c
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@@ -11,6 +11,7 @@
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*/
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#include <linux/pci.h>
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+#include <linux/module.h>
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#include <linux/ssb/ssb.h>
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#include "ssb_private.h"
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--- a/drivers/ssb/main.c
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+++ b/drivers/ssb/main.c
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@@ -12,6 +12,7 @@
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#include <linux/delay.h>
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#include <linux/io.h>
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+#include <linux/module.h>
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#include <linux/ssb/ssb.h>
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#include <linux/ssb/ssb_regs.h>
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#include <linux/ssb/ssb_driver_gige.h>
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@@ -1260,16 +1261,34 @@ void ssb_device_disable(struct ssb_devic
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}
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EXPORT_SYMBOL(ssb_device_disable);
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+/* Some chipsets need routing known for PCIe and 64-bit DMA */
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+static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
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+{
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+ u16 chip_id = dev->bus->chip_id;
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+
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+ if (dev->id.coreid == SSB_DEV_80211) {
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+ return (chip_id == 0x4322 || chip_id == 43221 ||
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+ chip_id == 43231 || chip_id == 43222);
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+ }
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+
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+ return 0;
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+}
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+
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u32 ssb_dma_translation(struct ssb_device *dev)
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{
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switch (dev->bus->bustype) {
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case SSB_BUSTYPE_SSB:
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return 0;
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case SSB_BUSTYPE_PCI:
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- if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64)
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+ if (pci_is_pcie(dev->bus->host_pci) &&
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+ ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
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return SSB_PCIE_DMA_H32;
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- else
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- return SSB_PCI_DMA;
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+ } else {
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+ if (ssb_dma_translation_special_bit(dev))
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+ return SSB_PCIE_DMA_H32;
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+ else
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+ return SSB_PCI_DMA;
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+ }
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default:
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__ssb_dma_not_implemented(dev);
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}
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--- a/drivers/ssb/pci.c
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+++ b/drivers/ssb/pci.c
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@@ -607,6 +607,29 @@ static void sprom_extract_r8(struct ssb_
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memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
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sizeof(out->antenna_gain.ghz5));
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+ /* Extract FEM info */
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+ SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
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+ SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
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+ SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
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+ SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
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+ SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
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+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
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+
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+ SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
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+ SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
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+ SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
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+ SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
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+ SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
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+ SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
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+
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sprom_extract_r458(out, in);
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/* TODO - get remaining rev 8 stuff needed */
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--- a/include/linux/ssb/ssb.h
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+++ b/include/linux/ssb/ssb.h
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@@ -25,7 +25,7 @@ struct ssb_sprom {
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u8 et1phyaddr; /* MII address for enet1 */
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u8 et0mdcport; /* MDIO for enet0 */
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u8 et1mdcport; /* MDIO for enet1 */
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- u8 board_rev; /* Board revision number from SPROM. */
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+ u16 board_rev; /* Board revision number from SPROM. */
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u8 country_code; /* Country Code */
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u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
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u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
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@@ -94,6 +94,15 @@ struct ssb_sprom {
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} ghz5; /* 5GHz band */
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} antenna_gain;
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+ struct {
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+ struct {
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+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
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+ } ghz2;
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+ struct {
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+ u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
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+ } ghz5;
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+ } fem;
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+
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/* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
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};
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@@ -231,10 +240,9 @@ struct ssb_driver {
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#define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
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extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
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-static inline int ssb_driver_register(struct ssb_driver *drv)
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-{
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- return __ssb_driver_register(drv, THIS_MODULE);
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-}
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+#define ssb_driver_register(drv) \
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+ __ssb_driver_register(drv, THIS_MODULE)
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+
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extern void ssb_driver_unregister(struct ssb_driver *drv);
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--- a/include/linux/ssb/ssb_regs.h
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+++ b/include/linux/ssb/ssb_regs.h
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@@ -432,6 +432,23 @@
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#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
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#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
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#define SSB_SPROM8_RXPO5G_SHIFT 8
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+#define SSB_SPROM8_FEM2G 0x00AE
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+#define SSB_SPROM8_FEM5G 0x00B0
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+#define SSB_SROM8_FEM_TSSIPOS 0x0001
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+#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
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+#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
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+#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
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+#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
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+#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
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+#define SSB_SROM8_FEM_TR_ISO 0x0700
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+#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
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+#define SSB_SROM8_FEM_ANTSWLUT 0xF800
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+#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
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+#define SSB_SPROM8_THERMAL 0x00B2
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+#define SSB_SPROM8_MPWR_RAWTS 0x00B4
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+#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
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+#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
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+#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
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#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
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#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
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#define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
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@@ -462,6 +479,46 @@
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#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
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#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
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+/* Values for boardflags_lo read from SPROM */
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+#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
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+#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
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+#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
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+#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
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+#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
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+#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
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+#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
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+#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
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+#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
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+#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
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+#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
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+#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
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+#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
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+#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
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+#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
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+#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
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+
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+/* Values for boardflags_hi read from SPROM */
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+#define SSB_BFH_NOPA 0x0001 /* has no PA */
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+#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
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+#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
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+#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
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+#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
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+#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
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+#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
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+
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+/* Values for boardflags2_lo read from SPROM */
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+#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
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+#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
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+#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
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+#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
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+#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
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+#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
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+#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
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+#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
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+#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
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+#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
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+#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
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+
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/* Values for SSB_SPROM1_BINF_CCODE */
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enum {
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SSB_SPROM1CCODE_WORLD = 0,
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