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537b423d9f
Remove patches adding support for MT7621 which have been merged upsteam. Patches for MT7981 and MT7986 have been merged too, but not in time to be included in the 2022.10 release, so we have to keep carrying them until the 2023.01 release. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
77 lines
3.0 KiB
Diff
77 lines
3.0 KiB
Diff
From a2df2df6fd1aec32572c7b30ccf5a184ec1763fd Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 27 Jul 2022 16:32:17 +0800
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Subject: [PATCH 56/71] mtd: spi-nor: add more flash ids
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Add more spi-nor flash ids
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/mtd/spi/spi-nor-core.c | 1 +
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drivers/mtd/spi/spi-nor-ids.c | 23 ++++++++++++++++++++++-
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2 files changed, 23 insertions(+), 1 deletion(-)
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--- a/drivers/mtd/spi/spi-nor-core.c
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+++ b/drivers/mtd/spi/spi-nor-core.c
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@@ -648,6 +648,7 @@ static int set_4byte(struct spi_nor *nor
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case SNOR_MFR_ISSI:
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case SNOR_MFR_MACRONIX:
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case SNOR_MFR_WINBOND:
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+ case SNOR_MFR_EON:
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if (need_wren)
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write_enable(nor);
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--- a/drivers/mtd/spi/spi-nor-ids.c
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+++ b/drivers/mtd/spi/spi-nor-ids.c
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@@ -83,7 +83,8 @@ const struct flash_info spi_nor_ids[] =
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{ INFO("en25q32b", 0x1c3016, 0, 64 * 1024, 64, 0) },
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{ INFO("en25q64", 0x1c3017, 0, 64 * 1024, 128, SECT_4K) },
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{ INFO("en25q128b", 0x1c3018, 0, 64 * 1024, 256, 0) },
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- { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, 0) },
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+ { INFO("en25qh128", 0x1c7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ { INFO("en25qh256", 0x1c7019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("en25s64", 0x1c3817, 0, 64 * 1024, 128, SECT_4K) },
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#endif
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#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
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@@ -119,6 +120,11 @@ const struct flash_info spi_nor_ids[] =
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{
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+ INFO("gd25q256", 0xc84019, 0, 64 * 1024, 512,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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+ {
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INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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@@ -395,6 +401,16 @@ const struct flash_info spi_nor_ids[] =
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{
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+ INFO("w25q256jv", 0xef7019, 0, 64 * 1024, 512,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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+ {
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+ INFO("w25q512jv", 0xef7020, 0, 64 * 1024, 1024,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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+ {
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INFO("w25q128jw", 0xef8018, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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@@ -439,6 +455,11 @@ const struct flash_info spi_nor_ids[] =
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SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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},
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{ INFO("w25q256", 0xef4019, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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+ {
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+ INFO("w25q512", 0xef4020, 0, 64 * 1024, 1024,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ |
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+ SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB)
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+ },
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{ INFO("w25m512jw", 0xef6119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("w25m512jv", 0xef7119, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ INFO("w25h02jv", 0xef9022, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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