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0ea329fec4
Weijie Gao has submitted an updated version of the patchset adding support for MT7986 and MT7981 to U-Boot. Use that v2 patchset. Changes of v2: - Add cpu driver for print_cpuinfo() - Fix NULL pointer dereference in mtk_image (was already fixed in OpenWrt) - Fix coding style - Minor changes https://patchwork.ozlabs.org/project/uboot/list/?series=316148 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
133 lines
4.4 KiB
Diff
133 lines
4.4 KiB
Diff
From 9a10182f21cc4007f46284d5c64c49dc892336be Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 31 Aug 2022 19:04:12 +0800
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Subject: [PATCH 05/32] mmc: mediatek: add support for MediaTek MT7891/MT7986
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SoCs
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Add eMMC and SDXC support for MediaTek MT7981/MT7986 SoCs
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Both chips support SDXC and eMMC 4.5. MT7986A supports eMMC 5.1.
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Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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drivers/mmc/mtk-sd.c | 68 ++++++++++++++++++++++++++++++++++----------
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1 file changed, 53 insertions(+), 15 deletions(-)
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--- a/drivers/mmc/mtk-sd.c
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+++ b/drivers/mmc/mtk-sd.c
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@@ -1496,7 +1496,12 @@ static void msdc_init_hw(struct msdc_hos
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/* Enable data & cmd interrupts */
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writel(DATA_INTS_MASK | CMD_INTS_MASK, &host->base->msdc_inten);
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- writel(0, tune_reg);
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+ if (host->top_base) {
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+ writel(0, &host->top_base->emmc_top_control);
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+ writel(0, &host->top_base->emmc_top_cmd);
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+ } else {
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+ writel(0, tune_reg);
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+ }
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writel(0, &host->base->msdc_iocon);
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if (host->r_smpl)
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@@ -1507,9 +1512,14 @@ static void msdc_init_hw(struct msdc_hos
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writel(0x403c0046, &host->base->patch_bit0);
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writel(0xffff4089, &host->base->patch_bit1);
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- if (host->dev_comp->stop_clk_fix)
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+ if (host->dev_comp->stop_clk_fix) {
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clrsetbits_le32(&host->base->patch_bit1, MSDC_PB1_STOP_DLY_M,
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3 << MSDC_PB1_STOP_DLY_S);
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+ clrbits_le32(&host->base->sdc_fifo_cfg,
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+ SDC_FIFO_CFG_WRVALIDSEL);
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+ clrbits_le32(&host->base->sdc_fifo_cfg,
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+ SDC_FIFO_CFG_RDVALIDSEL);
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+ }
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if (host->dev_comp->busy_check)
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clrbits_le32(&host->base->patch_bit1, (1 << 7));
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@@ -1544,15 +1554,28 @@ static void msdc_init_hw(struct msdc_hos
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}
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if (host->dev_comp->data_tune) {
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- setbits_le32(tune_reg,
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- MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
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- clrsetbits_le32(&host->base->patch_bit0,
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- MSDC_INT_DAT_LATCH_CK_SEL_M,
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- host->latch_ck <<
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- MSDC_INT_DAT_LATCH_CK_SEL_S);
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+ if (host->top_base) {
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+ setbits_le32(&host->top_base->emmc_top_control,
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+ PAD_DAT_RD_RXDLY_SEL);
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+ clrbits_le32(&host->top_base->emmc_top_control,
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+ DATA_K_VALUE_SEL);
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+ setbits_le32(&host->top_base->emmc_top_cmd,
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+ PAD_CMD_RD_RXDLY_SEL);
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+ } else {
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+ setbits_le32(tune_reg,
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+ MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL);
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+ clrsetbits_le32(&host->base->patch_bit0,
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+ MSDC_INT_DAT_LATCH_CK_SEL_M,
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+ host->latch_ck <<
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+ MSDC_INT_DAT_LATCH_CK_SEL_S);
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+ }
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} else {
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/* choose clock tune */
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- setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
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+ if (host->top_base)
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+ setbits_le32(&host->top_base->emmc_top_control,
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+ PAD_RXDLY_SEL);
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+ else
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+ setbits_le32(tune_reg, MSDC_PAD_TUNE_RXDLYSEL);
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}
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if (host->dev_comp->builtin_pad_ctrl) {
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@@ -1604,12 +1627,6 @@ static void msdc_init_hw(struct msdc_hos
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clrsetbits_le32(&host->base->sdc_cfg, SDC_CFG_DTOC_M,
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3 << SDC_CFG_DTOC_S);
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- if (host->dev_comp->stop_clk_fix) {
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- clrbits_le32(&host->base->sdc_fifo_cfg,
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- SDC_FIFO_CFG_WRVALIDSEL);
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- clrbits_le32(&host->base->sdc_fifo_cfg,
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- SDC_FIFO_CFG_RDVALIDSEL);
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- }
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host->def_tune_para.iocon = readl(&host->base->msdc_iocon);
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host->def_tune_para.pad_tune = readl(&host->base->pad_tune);
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@@ -1792,6 +1809,25 @@ static const struct msdc_compatible mt76
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.enhance_rx = false
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};
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+static const struct msdc_compatible mt7986_compat = {
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+ .clk_div_bits = 12,
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+ .pad_tune0 = true,
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+ .async_fifo = true,
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+ .data_tune = true,
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+ .busy_check = true,
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+ .stop_clk_fix = true,
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+ .enhance_rx = true,
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+};
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+
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+static const struct msdc_compatible mt7981_compat = {
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+ .clk_div_bits = 12,
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+ .pad_tune0 = true,
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+ .async_fifo = true,
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+ .data_tune = true,
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+ .busy_check = true,
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+ .stop_clk_fix = true,
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+};
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+
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static const struct msdc_compatible mt8512_compat = {
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.clk_div_bits = 12,
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.pad_tune0 = true,
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@@ -1824,6 +1860,8 @@ static const struct udevice_id msdc_ids[
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{ .compatible = "mediatek,mt7621-mmc", .data = (ulong)&mt7621_compat },
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{ .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
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{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
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+ { .compatible = "mediatek,mt7986-mmc", .data = (ulong)&mt7986_compat },
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+ { .compatible = "mediatek,mt7981-mmc", .data = (ulong)&mt7981_compat },
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{ .compatible = "mediatek,mt8512-mmc", .data = (ulong)&mt8512_compat },
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{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
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{ .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
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