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https://github.com/openwrt/openwrt.git
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537b423d9f
Remove patches adding support for MT7621 which have been merged upsteam. Patches for MT7981 and MT7986 have been merged too, but not in time to be included in the 2022.10 release, so we have to keep carrying them until the 2023.01 release. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
1149 lines
24 KiB
Diff
1149 lines
24 KiB
Diff
From bad27c737d27f8afc4d597b6de1bdbc26a152ad9 Mon Sep 17 00:00:00 2001
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From: Weijie Gao <weijie.gao@mediatek.com>
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Date: Wed, 31 Aug 2022 19:00:22 +0800
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Subject: [PATCH 03/32] board: mediatek: add MT7986 reference boards
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Add general board files based on MT7986 SoCs.
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MT7986 uses one mmc controller for booting from both SD and eMMC.
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Both MT7986A and MT7986B use the same pins for spi controller.
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Configs for various boot types:
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1. mt7986_rfb_defconfig - SPI-NOR and SPI-NAND for MT7986A/B
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2. mt7986a_bpir3_emmc_defconfig - eMMC for MT7986A only
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3. mt7986a_bpir3_sd_defconfig - SD for MT7986A only
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Reviewed-by: Simon Glass <sjg@chromium.org>
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Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
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---
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arch/arm/dts/Makefile | 6 +
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arch/arm/dts/mt7986a-emmc-rfb.dts | 16 ++
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arch/arm/dts/mt7986a-rfb.dts | 218 +++++++++++++++++++++++++++
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arch/arm/dts/mt7986a-sd-rfb.dts | 177 ++++++++++++++++++++++
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arch/arm/dts/mt7986b-emmc-rfb.dts | 16 ++
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arch/arm/dts/mt7986b-rfb.dts | 204 +++++++++++++++++++++++++
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arch/arm/dts/mt7986b-sd-rfb.dts | 173 +++++++++++++++++++++
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board/mediatek/mt7986/MAINTAINERS | 10 ++
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board/mediatek/mt7986/Makefile | 3 +
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board/mediatek/mt7986/mt7986_rfb.c | 10 ++
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configs/mt7986_rfb_defconfig | 66 ++++++++
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configs/mt7986a_bpir3_emmc_defconfig | 64 ++++++++
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configs/mt7986a_bpir3_sd_defconfig | 64 ++++++++
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include/configs/mt7986.h | 26 ++++
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14 files changed, 1053 insertions(+)
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create mode 100644 arch/arm/dts/mt7986a-emmc-rfb.dts
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create mode 100644 arch/arm/dts/mt7986a-rfb.dts
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create mode 100644 arch/arm/dts/mt7986a-sd-rfb.dts
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create mode 100644 arch/arm/dts/mt7986b-emmc-rfb.dts
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create mode 100644 arch/arm/dts/mt7986b-rfb.dts
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create mode 100644 arch/arm/dts/mt7986b-sd-rfb.dts
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create mode 100644 board/mediatek/mt7986/MAINTAINERS
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create mode 100644 board/mediatek/mt7986/Makefile
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create mode 100644 board/mediatek/mt7986/mt7986_rfb.c
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create mode 100644 configs/mt7986_rfb_defconfig
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create mode 100644 configs/mt7986a_bpir3_emmc_defconfig
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create mode 100644 configs/mt7986a_bpir3_sd_defconfig
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create mode 100644 include/configs/mt7986.h
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--- a/arch/arm/dts/Makefile
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+++ b/arch/arm/dts/Makefile
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@@ -1233,6 +1233,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
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mt7622-bananapi-bpi-r64.dtb \
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mt7623n-bananapi-bpi-r2.dtb \
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mt7629-rfb.dtb \
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+ mt7986a-rfb.dtb \
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+ mt7986b-rfb.dtb \
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+ mt7986a-sd-rfb.dtb \
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+ mt7986b-sd-rfb.dtb \
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+ mt7986a-emmc-rfb.dtb \
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+ mt7986b-emmc-rfb.dtb \
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mt8183-pumpkin.dtb \
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mt8512-bm1-emmc.dtb \
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mt8516-pumpkin.dtb \
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--- /dev/null
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+++ b/arch/arm/dts/mt7986a-emmc-rfb.dts
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@@ -0,0 +1,16 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+#include "mt7986a-rfb.dts"
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+
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+/ {
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+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
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+ "mediatek,mt7986-emmc-rfb";
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+ bl2_verify {
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+ bl2_compatible = "emmc";
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+ };
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+};
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--- /dev/null
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+++ b/arch/arm/dts/mt7986a-rfb.dts
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@@ -0,0 +1,218 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+#include "mt7986.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ model = "mt7986-rfb";
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+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
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+ chosen {
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+ stdout-path = &uart0;
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+ tick-timer = &timer0;
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+ };
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+
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+ reg_1p8v: regulator-1p8v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-1.8V";
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+ regulator-min-microvolt = <1800000>;
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+ regulator-max-microvolt = <1800000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart1_pins>;
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+ status = "disabled";
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+};
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+
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+ð {
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+ status = "okay";
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+ mediatek,gmac-id = <0>;
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+ phy-mode = "sgmii";
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+ mediatek,switch = "mt7531";
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+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+};
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+
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+&pinctrl {
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+ spi_flash_pins: spi0-pins-func-1 {
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+ mux {
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+ function = "flash";
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+ groups = "spi0", "spi0_wp_hold";
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+ };
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+
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+ conf-pu {
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+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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+ };
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+
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+ conf-pd {
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+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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+ };
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+ };
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+
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+ snfi_pins: snfi-pins-func-1 {
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+ mux {
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+ function = "flash";
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+ groups = "snfi";
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+ };
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+
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+ clk {
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+ pins = "SPI0_CLK";
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
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+ };
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+
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+ conf-pu {
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+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
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+ drive-strength = <MTK_DRIVE_6mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
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+ };
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+
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+ conf-pd {
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+ pins = "SPI0_MOSI", "SPI0_MISO";
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+ drive-strength = <MTK_DRIVE_6mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
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+ };
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+ };
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+
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+ spic_pins: spi1-pins-func-1 {
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+ mux {
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+ function = "spi";
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+ groups = "spi1_2";
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+ };
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+ };
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+
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+ uart1_pins: spi1-pins-func-3 {
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+ mux {
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+ function = "uart";
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+ groups = "uart1_2";
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+ };
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+ };
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+
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+ pwm_pins: pwm0-pins-func-1 {
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+ mux {
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+ function = "pwm";
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+ groups = "pwm0";
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+ };
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+ };
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+
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+ mmc0_pins_default: mmc0default {
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+ mux {
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+ function = "flash";
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+ groups = "emmc_51";
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+ };
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+
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+ conf-cmd-dat {
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+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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+ input-enable;
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+ drive-strength = <MTK_DRIVE_4mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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+ };
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+
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+ conf-clk {
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+ pins = "EMMC_CK";
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+ drive-strength = <MTK_DRIVE_6mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+
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+ conf-dsl {
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+ pins = "EMMC_DSL";
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+
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+ conf-rst {
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+ pins = "EMMC_RSTB";
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+ drive-strength = <MTK_DRIVE_4mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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+ };
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+ };
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+};
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+
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+&snand {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&snfi_pins>;
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+ status = "okay";
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+ quad-spi;
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+};
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+
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+&spi0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi_flash_pins>;
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+ status = "okay";
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+ must_tx;
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+ enhance_timing;
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+ dma_ext;
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+ ipm_design;
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+ support_quad;
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+ tick_dly = <2>;
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+ sample_sel = <0>;
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+
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+ spi_nor@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <52000000>;
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+ };
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+
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+ spi_nand@1 {
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+ compatible = "spi-nand";
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+ reg = <1>;
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+ spi-max-frequency = <52000000>;
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+ };
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+};
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+
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+&pwm {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm_pins>;
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+ status = "okay";
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+};
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+
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+&watchdog {
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+ status = "disabled";
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+};
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+
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+&mmc0 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&mmc0_pins_default>;
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+ bus-width = <8>;
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+ max-frequency = <52000000>;
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+ cap-mmc-highspeed;
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+ cap-mmc-hw-reset;
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+ vmmc-supply = <®_3p3v>;
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+ vqmmc-supply = <®_1p8v>;
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+ non-removable;
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+ status = "okay";
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+};
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--- /dev/null
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+++ b/arch/arm/dts/mt7986a-sd-rfb.dts
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@@ -0,0 +1,177 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * Copyright (c) 2022 MediaTek Inc.
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+ * Author: Sam Shih <sam.shih@mediatek.com>
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+ */
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+
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+/dts-v1/;
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+#include "mt7986.dtsi"
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+#include <dt-bindings/gpio/gpio.h>
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+
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+/ {
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+ #address-cells = <1>;
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+ #size-cells = <1>;
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+ model = "mt7986-rfb";
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+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
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+ "mediatek,mt7986-sd-rfb";
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+ chosen {
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+ stdout-path = &uart0;
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+ tick-timer = &timer0;
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+ };
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+
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+ reg_3p3v: regulator-3p3v {
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+ compatible = "regulator-fixed";
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+ regulator-name = "fixed-3.3V";
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+ regulator-min-microvolt = <3300000>;
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+ regulator-max-microvolt = <3300000>;
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+ regulator-boot-on;
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+ regulator-always-on;
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+ };
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+};
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+
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+&uart0 {
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+ status = "okay";
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+};
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+
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+&uart1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&uart1_pins>;
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+ status = "disabled";
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+};
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+
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+ð {
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+ status = "okay";
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+ mediatek,gmac-id = <0>;
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+ phy-mode = "sgmii";
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+ mediatek,switch = "mt7531";
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+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
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+
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+ fixed-link {
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+ speed = <1000>;
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+ full-duplex;
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+ };
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+};
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+
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+&pinctrl {
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+ spi_flash_pins: spi0-pins-func-1 {
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+ mux {
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+ function = "flash";
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+ groups = "spi0", "spi0_wp_hold";
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+ };
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+
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+ conf-pu {
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+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
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+ };
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+
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+ conf-pd {
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+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
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+ drive-strength = <MTK_DRIVE_8mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
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+ };
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+ };
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+
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+ spic_pins: spi1-pins-func-1 {
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+ mux {
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+ function = "spi";
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+ groups = "spi1_2";
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+ };
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+ };
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+
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+ uart1_pins: spi1-pins-func-3 {
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+ mux {
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+ function = "uart";
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+ groups = "uart1_2";
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+ };
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+ };
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+
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+ pwm_pins: pwm0-pins-func-1 {
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+ mux {
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+ function = "pwm";
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+ groups = "pwm0";
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+ };
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+ };
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+
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+ mmc0_pins_default: mmc0default {
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+ mux {
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+ function = "flash";
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+ groups = "emmc_51";
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+ };
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+
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+ conf-cmd-dat {
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+ pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
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+ "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
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+ "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
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+ input-enable;
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+ drive-strength = <MTK_DRIVE_4mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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+ };
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+
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+ conf-clk {
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+ pins = "EMMC_CK";
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+ drive-strength = <MTK_DRIVE_6mA>;
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+
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+ conf-dsl {
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+ pins = "EMMC_DSL";
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+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
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+ };
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+
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+ conf-rst {
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+ pins = "EMMC_RSTB";
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+ drive-strength = <MTK_DRIVE_4mA>;
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+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
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+ };
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+ };
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+};
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+
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+&spi0 {
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+ #address-cells = <1>;
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+ #size-cells = <0>;
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&spi_flash_pins>;
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+ status = "okay";
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+ must_tx;
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+ enhance_timing;
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+ dma_ext;
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+ ipm_design;
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+ support_quad;
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+ tick_dly = <2>;
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+ sample_sel = <0>;
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+
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+ spi_nor@0 {
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+ compatible = "jedec,spi-nor";
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+ reg = <0>;
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+ spi-max-frequency = <52000000>;
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+ };
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+
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+ spi_nand@1 {
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+ compatible = "spi-nand";
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+ reg = <1>;
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+ spi-max-frequency = <52000000>;
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+ };
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+};
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+
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+&pwm {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pwm_pins>;
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+ status = "okay";
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+};
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+
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+&watchdog {
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+ status = "disabled";
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+};
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+
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|
+&mmc0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc0_pins_default>;
|
|
+ bus-width = <4>;
|
|
+ max-frequency = <52000000>;
|
|
+ cap-sd-highspeed;
|
|
+ r_smpl = <1>;
|
|
+ vmmc-supply = <®_3p3v>;
|
|
+ vqmmc-supply = <®_3p3v>;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/mt7986b-emmc-rfb.dts
|
|
@@ -0,0 +1,16 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (c) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "mt7986a-rfb.dts"
|
|
+
|
|
+/ {
|
|
+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
|
|
+ "mediatek,mt7986-emmc-rfb";
|
|
+ bl2_verify {
|
|
+ bl2_compatible = "emmc";
|
|
+ };
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/mt7986b-rfb.dts
|
|
@@ -0,0 +1,204 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (c) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "mt7986.dtsi"
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+/ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ model = "mt7986-rfb";
|
|
+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb";
|
|
+ chosen {
|
|
+ stdout-path = &uart0;
|
|
+ tick-timer = &timer0;
|
|
+ };
|
|
+
|
|
+ reg_3p3v: regulator-3p3v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "fixed-3.3V";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1_pins>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+ð {
|
|
+ status = "okay";
|
|
+ mediatek,gmac-id = <0>;
|
|
+ phy-mode = "sgmii";
|
|
+ mediatek,switch = "mt7531";
|
|
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ spi_flash_pins: spi0-pins-func-1 {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
+ };
|
|
+
|
|
+ conf-pu {
|
|
+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
|
+ };
|
|
+
|
|
+ conf-pd {
|
|
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ snfi_pins: snfi-pins-func-1 {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "snfi";
|
|
+ };
|
|
+
|
|
+ clk {
|
|
+ pins = "SPI0_CLK";
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
|
|
+ };
|
|
+
|
|
+ conf-pu {
|
|
+ pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
|
|
+ drive-strength = <MTK_DRIVE_6mA>;
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_00>;
|
|
+ };
|
|
+
|
|
+ conf-pd {
|
|
+ pins = "SPI0_MOSI", "SPI0_MISO";
|
|
+ drive-strength = <MTK_DRIVE_6mA>;
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_00>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spic_pins: spi1-pins-func-1 {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi1_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart1_pins: spi1-pins-func-3 {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart1_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm_pins: pwm0-pins-func-1 {
|
|
+ mux {
|
|
+ function = "pwm";
|
|
+ groups = "pwm0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mmc0_pins_default: mmc0default {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "emmc_45";
|
|
+ input-schmitt-enable;
|
|
+ };
|
|
+
|
|
+ conf-cmd-dat {
|
|
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
|
|
+ "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
|
|
+ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
|
|
+ input-enable;
|
|
+ drive-strength = <MTK_DRIVE_4mA>;
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
+ };
|
|
+
|
|
+ conf-clk {
|
|
+ pins = "SPI1_CS";
|
|
+ drive-strength = <MTK_DRIVE_6mA>;
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
|
+ };
|
|
+
|
|
+ conf-rst {
|
|
+ pins = "PWM1";
|
|
+ drive-strength = <MTK_DRIVE_4mA>;
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&snand {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&snfi_pins>;
|
|
+ status = "okay";
|
|
+ quad-spi;
|
|
+};
|
|
+
|
|
+&spi0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi_flash_pins>;
|
|
+ status = "okay";
|
|
+ must_tx;
|
|
+ enhance_timing;
|
|
+ dma_ext;
|
|
+ ipm_design;
|
|
+ support_quad;
|
|
+ tick_dly = <2>;
|
|
+ sample_sel = <0>;
|
|
+
|
|
+ spi_nor@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ };
|
|
+
|
|
+ spi_nand@1 {
|
|
+ compatible = "spi-nand";
|
|
+ reg = <1>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pwm {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm_pins>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&watchdog {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc0_pins_default>;
|
|
+ bus-width = <8>;
|
|
+ max-frequency = <52000000>;
|
|
+ cap-mmc-highspeed;
|
|
+ cap-mmc-hw-reset;
|
|
+ vmmc-supply = <®_3p3v>;
|
|
+ non-removable;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/arch/arm/dts/mt7986b-sd-rfb.dts
|
|
@@ -0,0 +1,173 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (c) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+/dts-v1/;
|
|
+#include "mt7986.dtsi"
|
|
+#include <dt-bindings/gpio/gpio.h>
|
|
+
|
|
+/ {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ model = "mt7986-rfb";
|
|
+ compatible = "mediatek,mt7986", "mediatek,mt7986-rfb",
|
|
+ "mediatek,mt7986-sd-rfb";
|
|
+ chosen {
|
|
+ stdout-path = &uart0;
|
|
+ tick-timer = &timer0;
|
|
+ };
|
|
+
|
|
+ reg_3p3v: regulator-3p3v {
|
|
+ compatible = "regulator-fixed";
|
|
+ regulator-name = "fixed-3.3V";
|
|
+ regulator-min-microvolt = <3300000>;
|
|
+ regulator-max-microvolt = <3300000>;
|
|
+ regulator-boot-on;
|
|
+ regulator-always-on;
|
|
+ };
|
|
+};
|
|
+
|
|
+&uart0 {
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&uart1 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&uart1_pins>;
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+ð {
|
|
+ status = "okay";
|
|
+ mediatek,gmac-id = <0>;
|
|
+ phy-mode = "sgmii";
|
|
+ mediatek,switch = "mt7531";
|
|
+ reset-gpios = <&gpio 5 GPIO_ACTIVE_HIGH>;
|
|
+
|
|
+ fixed-link {
|
|
+ speed = <1000>;
|
|
+ full-duplex;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pinctrl {
|
|
+ spi_flash_pins: spi0-pins-func-1 {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "spi0", "spi0_wp_hold";
|
|
+ };
|
|
+
|
|
+ conf-pu {
|
|
+ pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP";
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
|
|
+ };
|
|
+
|
|
+ conf-pd {
|
|
+ pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO";
|
|
+ drive-strength = <MTK_DRIVE_8mA>;
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+ spic_pins: spi1-pins-func-1 {
|
|
+ mux {
|
|
+ function = "spi";
|
|
+ groups = "spi1_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ uart1_pins: spi1-pins-func-3 {
|
|
+ mux {
|
|
+ function = "uart";
|
|
+ groups = "uart1_2";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ pwm_pins: pwm0-pins-func-1 {
|
|
+ mux {
|
|
+ function = "pwm";
|
|
+ groups = "pwm0";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ mmc0_pins_default: mmc0default {
|
|
+ mux {
|
|
+ function = "flash";
|
|
+ groups = "emmc_45";
|
|
+ input-schmitt-enable;
|
|
+ };
|
|
+
|
|
+ conf-cmd-dat {
|
|
+ pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO",
|
|
+ "SPI0_CS", "SPI0_HOLD", "SPI0_WP",
|
|
+ "SPI1_CLK", "SPI1_MOSI", "SPI1_MISO";
|
|
+ input-enable;
|
|
+ drive-strength = <MTK_DRIVE_4mA>;
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
+ };
|
|
+
|
|
+ conf-clk {
|
|
+ pins = "SPI1_CS";
|
|
+ drive-strength = <MTK_DRIVE_6mA>;
|
|
+ bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
|
|
+ };
|
|
+
|
|
+ conf-rst {
|
|
+ pins = "PWM1";
|
|
+ drive-strength = <MTK_DRIVE_4mA>;
|
|
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
|
|
+ };
|
|
+ };
|
|
+};
|
|
+
|
|
+&spi0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&spi_flash_pins>;
|
|
+ status = "okay";
|
|
+ must_tx;
|
|
+ enhance_timing;
|
|
+ dma_ext;
|
|
+ ipm_design;
|
|
+ support_quad;
|
|
+ tick_dly = <2>;
|
|
+ sample_sel = <0>;
|
|
+
|
|
+ spi_nor@0 {
|
|
+ compatible = "jedec,spi-nor";
|
|
+ reg = <0>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ };
|
|
+
|
|
+ spi_nand@1 {
|
|
+ compatible = "spi-nand";
|
|
+ reg = <1>;
|
|
+ spi-max-frequency = <52000000>;
|
|
+ };
|
|
+};
|
|
+
|
|
+&pwm {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&pwm_pins>;
|
|
+ status = "okay";
|
|
+};
|
|
+
|
|
+&watchdog {
|
|
+ status = "disabled";
|
|
+};
|
|
+
|
|
+&mmc0 {
|
|
+ pinctrl-names = "default";
|
|
+ pinctrl-0 = <&mmc0_pins_default>;
|
|
+ bus-width = <4>;
|
|
+ max-frequency = <52000000>;
|
|
+ cap-sd-highspeed;
|
|
+ r_smpl = <1>;
|
|
+ vmmc-supply = <®_3p3v>;
|
|
+ vqmmc-supply = <®_3p3v>;
|
|
+ status = "okay";
|
|
+};
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7986/MAINTAINERS
|
|
@@ -0,0 +1,10 @@
|
|
+MT7986
|
|
+M: Sam Shih <sam.shih@mediatek.com>
|
|
+S: Maintained
|
|
+F: board/mediatek/mt7986
|
|
+F: include/configs/mt7986.h
|
|
+F: configs/mt7986_rfb_defconfig
|
|
+F: configs/mt7986a_emmc_rfb_defconfig
|
|
+F: configs/mt7986a_sd_rfb_defconfig
|
|
+F: configs/mt7986b_emmc_rfb_defconfig
|
|
+F: configs/mt7986b_sd_rfb_defconfig
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7986/Makefile
|
|
@@ -0,0 +1,3 @@
|
|
+# SPDX-License-Identifier: GPL-2.0
|
|
+
|
|
+obj-y += mt7986_rfb.o
|
|
--- /dev/null
|
|
+++ b/board/mediatek/mt7986/mt7986_rfb.c
|
|
@@ -0,0 +1,10 @@
|
|
+// SPDX-License-Identifier: GPL-2.0
|
|
+/*
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+int board_init(void)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
--- /dev/null
|
|
+++ b/configs/mt7986_rfb_defconfig
|
|
@@ -0,0 +1,66 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_POSITION_INDEPENDENT=y
|
|
+CONFIG_ARCH_MEDIATEK=y
|
|
+CONFIG_SYS_TEXT_BASE=0x41e00000
|
|
+CONFIG_SYS_MALLOC_F_LEN=0x4000
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-rfb"
|
|
+CONFIG_TARGET_MT7986=y
|
|
+CONFIG_DEBUG_UART_BASE=0x11002000
|
|
+CONFIG_DEBUG_UART_CLOCK=40000000
|
|
+CONFIG_SYS_LOAD_ADDR=0x46000000
|
|
+CONFIG_DEBUG_UART=y
|
|
+# CONFIG_AUTOBOOT is not set
|
|
+CONFIG_DEFAULT_FDT_FILE="mt7986a-rfb"
|
|
+CONFIG_LOGLEVEL=7
|
|
+CONFIG_LOG=y
|
|
+CONFIG_SYS_PROMPT="MT7986> "
|
|
+CONFIG_SYS_CBSIZE=512
|
|
+CONFIG_SYS_PBSIZE=1049
|
|
+# CONFIG_BOOTM_NETBSD is not set
|
|
+# CONFIG_BOOTM_PLAN9 is not set
|
|
+# CONFIG_BOOTM_RTEMS is not set
|
|
+# CONFIG_BOOTM_VXWORKS is not set
|
|
+# CONFIG_CMD_ELF is not set
|
|
+# CONFIG_CMD_UNLZ4 is not set
|
|
+# CONFIG_CMD_UNZIP is not set
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_MTD=y
|
|
+CONFIG_CMD_SF_TEST=y
|
|
+CONFIG_CMD_PING=y
|
|
+CONFIG_CMD_SMC=y
|
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
|
+CONFIG_REGMAP=y
|
|
+CONFIG_SYSCON=y
|
|
+CONFIG_CLK=y
|
|
+# CONFIG_MMC is not set
|
|
+CONFIG_MTD=y
|
|
+CONFIG_DM_MTD=y
|
|
+CONFIG_MTD_SPI_NAND=y
|
|
+CONFIG_DM_SPI_FLASH=y
|
|
+CONFIG_SPI_FLASH_SFDP_SUPPORT=y
|
|
+CONFIG_SPI_FLASH_EON=y
|
|
+CONFIG_SPI_FLASH_GIGADEVICE=y
|
|
+CONFIG_SPI_FLASH_ISSI=y
|
|
+CONFIG_SPI_FLASH_MACRONIX=y
|
|
+CONFIG_SPI_FLASH_SPANSION=y
|
|
+CONFIG_SPI_FLASH_STMICRO=y
|
|
+CONFIG_SPI_FLASH_WINBOND=y
|
|
+CONFIG_SPI_FLASH_XMC=y
|
|
+CONFIG_SPI_FLASH_XTX=y
|
|
+CONFIG_SPI_FLASH_MTD=y
|
|
+CONFIG_PHY_FIXED=y
|
|
+CONFIG_DM_ETH=y
|
|
+CONFIG_MEDIATEK_ETH=y
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCONF=y
|
|
+CONFIG_PINCTRL_MT7986=y
|
|
+CONFIG_POWER_DOMAIN=y
|
|
+CONFIG_MTK_POWER_DOMAIN=y
|
|
+CONFIG_DM_SERIAL=y
|
|
+CONFIG_MTK_SERIAL=y
|
|
+CONFIG_SPI=y
|
|
+CONFIG_DM_SPI=y
|
|
+CONFIG_MTK_SPIM=y
|
|
+CONFIG_HEXDUMP=y
|
|
--- /dev/null
|
|
+++ b/configs/mt7986a_bpir3_emmc_defconfig
|
|
@@ -0,0 +1,64 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_POSITION_INDEPENDENT=y
|
|
+CONFIG_ARCH_MEDIATEK=y
|
|
+CONFIG_SYS_TEXT_BASE=0x41e00000
|
|
+CONFIG_SYS_MALLOC_F_LEN=0x4000
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_ENV_SIZE=0x80000
|
|
+CONFIG_ENV_OFFSET=0x300000
|
|
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-emmc-rfb"
|
|
+CONFIG_TARGET_MT7986=y
|
|
+CONFIG_DEBUG_UART_BASE=0x11002000
|
|
+CONFIG_DEBUG_UART_CLOCK=40000000
|
|
+CONFIG_SYS_LOAD_ADDR=0x46000000
|
|
+CONFIG_DEBUG_UART=y
|
|
+# CONFIG_AUTOBOOT is not set
|
|
+CONFIG_DEFAULT_FDT_FILE="mt7986a-emmc-rfb"
|
|
+CONFIG_LOGLEVEL=7
|
|
+CONFIG_LOG=y
|
|
+CONFIG_SYS_PROMPT="MT7986> "
|
|
+CONFIG_SYS_CBSIZE=512
|
|
+CONFIG_SYS_PBSIZE=1049
|
|
+# CONFIG_BOOTM_NETBSD is not set
|
|
+# CONFIG_BOOTM_PLAN9 is not set
|
|
+# CONFIG_BOOTM_RTEMS is not set
|
|
+# CONFIG_BOOTM_VXWORKS is not set
|
|
+# CONFIG_CMD_ELF is not set
|
|
+# CONFIG_CMD_UNLZ4 is not set
|
|
+# CONFIG_CMD_UNZIP is not set
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_GPT=y
|
|
+CONFIG_CMD_GPT_RENAME=y
|
|
+CONFIG_CMD_LSBLK=y
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_PART=y
|
|
+CONFIG_CMD_READ=y
|
|
+CONFIG_CMD_PING=y
|
|
+CONFIG_CMD_SMC=y
|
|
+CONFIG_CMD_FAT=y
|
|
+CONFIG_CMD_FS_GENERIC=y
|
|
+CONFIG_PARTITION_TYPE_GUID=y
|
|
+CONFIG_ENV_OVERWRITE=y
|
|
+CONFIG_ENV_IS_IN_MMC=y
|
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
|
+CONFIG_REGMAP=y
|
|
+CONFIG_SYSCON=y
|
|
+CONFIG_CLK=y
|
|
+CONFIG_MMC_HS200_SUPPORT=y
|
|
+CONFIG_MMC_MTK=y
|
|
+CONFIG_PHY_FIXED=y
|
|
+CONFIG_DM_ETH=y
|
|
+CONFIG_MEDIATEK_ETH=y
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCONF=y
|
|
+CONFIG_PINCTRL_MT7986=y
|
|
+CONFIG_POWER_DOMAIN=y
|
|
+CONFIG_MTK_POWER_DOMAIN=y
|
|
+CONFIG_DM_REGULATOR=y
|
|
+CONFIG_DM_REGULATOR_FIXED=y
|
|
+CONFIG_DM_SERIAL=y
|
|
+CONFIG_MTK_SERIAL=y
|
|
+CONFIG_FAT_WRITE=y
|
|
+CONFIG_HEXDUMP=y
|
|
+# CONFIG_EFI_LOADER is not set
|
|
--- /dev/null
|
|
+++ b/configs/mt7986a_bpir3_sd_defconfig
|
|
@@ -0,0 +1,64 @@
|
|
+CONFIG_ARM=y
|
|
+CONFIG_POSITION_INDEPENDENT=y
|
|
+CONFIG_ARCH_MEDIATEK=y
|
|
+CONFIG_SYS_TEXT_BASE=0x41e00000
|
|
+CONFIG_SYS_MALLOC_F_LEN=0x4000
|
|
+CONFIG_NR_DRAM_BANKS=1
|
|
+CONFIG_ENV_SIZE=0x80000
|
|
+CONFIG_ENV_OFFSET=0x300000
|
|
+CONFIG_DEFAULT_DEVICE_TREE="mt7986a-sd-rfb"
|
|
+CONFIG_TARGET_MT7986=y
|
|
+CONFIG_DEBUG_UART_BASE=0x11002000
|
|
+CONFIG_DEBUG_UART_CLOCK=40000000
|
|
+CONFIG_SYS_LOAD_ADDR=0x46000000
|
|
+CONFIG_DEBUG_UART=y
|
|
+# CONFIG_AUTOBOOT is not set
|
|
+CONFIG_DEFAULT_FDT_FILE="mt7986a-sd-rfb"
|
|
+CONFIG_LOGLEVEL=7
|
|
+CONFIG_LOG=y
|
|
+CONFIG_SYS_PROMPT="MT7986> "
|
|
+CONFIG_SYS_CBSIZE=512
|
|
+CONFIG_SYS_PBSIZE=1049
|
|
+# CONFIG_BOOTM_NETBSD is not set
|
|
+# CONFIG_BOOTM_PLAN9 is not set
|
|
+# CONFIG_BOOTM_RTEMS is not set
|
|
+# CONFIG_BOOTM_VXWORKS is not set
|
|
+# CONFIG_CMD_ELF is not set
|
|
+# CONFIG_CMD_UNLZ4 is not set
|
|
+# CONFIG_CMD_UNZIP is not set
|
|
+CONFIG_CMD_GPIO=y
|
|
+CONFIG_CMD_GPT=y
|
|
+CONFIG_CMD_GPT_RENAME=y
|
|
+CONFIG_CMD_LSBLK=y
|
|
+CONFIG_CMD_MMC=y
|
|
+CONFIG_CMD_PART=y
|
|
+CONFIG_CMD_READ=y
|
|
+CONFIG_CMD_PING=y
|
|
+CONFIG_CMD_SMC=y
|
|
+CONFIG_CMD_FAT=y
|
|
+CONFIG_CMD_FS_GENERIC=y
|
|
+CONFIG_PARTITION_TYPE_GUID=y
|
|
+CONFIG_ENV_OVERWRITE=y
|
|
+CONFIG_ENV_IS_IN_MMC=y
|
|
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
|
|
+CONFIG_NET_RANDOM_ETHADDR=y
|
|
+CONFIG_REGMAP=y
|
|
+CONFIG_SYSCON=y
|
|
+CONFIG_CLK=y
|
|
+CONFIG_MMC_HS200_SUPPORT=y
|
|
+CONFIG_MMC_MTK=y
|
|
+CONFIG_PHY_FIXED=y
|
|
+CONFIG_DM_ETH=y
|
|
+CONFIG_MEDIATEK_ETH=y
|
|
+CONFIG_PINCTRL=y
|
|
+CONFIG_PINCONF=y
|
|
+CONFIG_PINCTRL_MT7986=y
|
|
+CONFIG_POWER_DOMAIN=y
|
|
+CONFIG_MTK_POWER_DOMAIN=y
|
|
+CONFIG_DM_REGULATOR=y
|
|
+CONFIG_DM_REGULATOR_FIXED=y
|
|
+CONFIG_DM_SERIAL=y
|
|
+CONFIG_MTK_SERIAL=y
|
|
+CONFIG_FAT_WRITE=y
|
|
+CONFIG_HEXDUMP=y
|
|
+# CONFIG_EFI_LOADER is not set
|
|
--- /dev/null
|
|
+++ b/include/configs/mt7986.h
|
|
@@ -0,0 +1,26 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0 */
|
|
+/*
|
|
+ * Configuration for MediaTek MT7986 SoC
|
|
+ *
|
|
+ * Copyright (C) 2022 MediaTek Inc.
|
|
+ * Author: Sam Shih <sam.shih@mediatek.com>
|
|
+ */
|
|
+
|
|
+#ifndef __MT7986_H
|
|
+#define __MT7986_H
|
|
+
|
|
+#include <linux/sizes.h>
|
|
+
|
|
+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
|
|
+#define CONFIG_SYS_MMC_ENV_DEV 0
|
|
+
|
|
+/* Uboot definition */
|
|
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
|
|
+
|
|
+/* SPL -> Uboot */
|
|
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
|
|
+
|
|
+/* DRAM */
|
|
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
|
|
+
|
|
+#endif
|