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b998d4fa51
SVN-Revision: 9815
609 lines
14 KiB
C
609 lines
14 KiB
C
/*
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* Driver for DANUBEASC serial ports
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*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Copyright (C) 2004 Infineon IFAP DC COM CPE
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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*/
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#include <linux/module.h>
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#include <linux/errno.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/interrupt.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/major.h>
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#include <linux/string.h>
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#include <linux/fcntl.h>
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#include <linux/ptrace.h>
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#include <linux/ioport.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/init.h>
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#include <linux/circ_buf.h>
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#include <linux/serial.h>
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#include <linux/serial_core.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/irq.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#include <asm/uaccess.h>
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#include <asm/bitops.h>
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#include <asm/danube/danube.h>
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#include <asm/danube/danube_irq.h>
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#include <asm/danube/danube_serial.h>
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#define PORT_DANUBEASC 111
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#include <linux/serial_core.h>
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#define UART_DUMMY_UER_RX 1
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static void danubeasc_tx_chars(struct uart_port *port);
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extern void prom_printf(const char * fmt, ...);
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static struct uart_port danubeasc_port;
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static struct uart_driver danubeasc_reg;
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static unsigned int uartclk = 0;
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extern unsigned int danube_get_fpi_hz(void);
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static void
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danubeasc_stop_tx (struct uart_port *port)
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{
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/* fifo underrun shuts up after firing once */
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return;
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}
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static void
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danubeasc_start_tx (struct uart_port *port)
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{
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unsigned long flags;
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local_irq_save(flags);
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danubeasc_tx_chars(port);
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local_irq_restore(flags);
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return;
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}
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static void
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danubeasc_stop_rx (struct uart_port *port)
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{
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/* clear the RX enable bit */
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writel(ASCWHBSTATE_CLRREN, DANUBE_ASC1_WHBSTATE);
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}
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static void
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danubeasc_enable_ms (struct uart_port *port)
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{
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/* no modem signals */
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return;
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}
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static void
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danubeasc_rx_chars (struct uart_port *port)
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{
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struct tty_struct *tty = port->info->tty;
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unsigned int ch = 0, rsr = 0, fifocnt;
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fifocnt = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_RXFFLMASK;
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while (fifocnt--)
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{
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u8 flag = TTY_NORMAL;
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ch = readl(DANUBE_ASC1_RBUF);
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rsr = (readl(DANUBE_ASC1_STATE) & ASCSTATE_ANY) | UART_DUMMY_UER_RX;
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tty_flip_buffer_push(tty);
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port->icount.rx++;
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/*
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* Note that the error handling code is
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* out of the main execution path
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*/
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if (rsr & ASCSTATE_ANY) {
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if (rsr & ASCSTATE_PE) {
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port->icount.parity++;
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writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE, DANUBE_ASC1_WHBSTATE);
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} else if (rsr & ASCSTATE_FE) {
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port->icount.frame++;
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writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRFE, DANUBE_ASC1_WHBSTATE);
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}
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if (rsr & ASCSTATE_ROE) {
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port->icount.overrun++;
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writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
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}
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rsr &= port->read_status_mask;
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if (rsr & ASCSTATE_PE)
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flag = TTY_PARITY;
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else if (rsr & ASCSTATE_FE)
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flag = TTY_FRAME;
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}
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if ((rsr & port->ignore_status_mask) == 0)
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tty_insert_flip_char(tty, ch, flag);
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if (rsr & ASCSTATE_ROE)
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/*
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* Overrun is special, since it's reported
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* immediately, and doesn't affect the current
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* character
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*/
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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}
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if (ch != 0)
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tty_flip_buffer_push(tty);
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return;
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}
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static void
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danubeasc_tx_chars (struct uart_port *port)
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{
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struct circ_buf *xmit = &port->info->xmit;
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if (uart_tx_stopped(port)) {
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danubeasc_stop_tx(port);
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return;
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}
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while(((readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
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>> ASCFSTAT_TXFFLOFF) != DANUBEASC_TXFIFO_FULL)
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{
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if (port->x_char) {
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writel(port->x_char, DANUBE_ASC1_TBUF);
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port->icount.tx++;
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port->x_char = 0;
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continue;
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}
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if (uart_circ_empty(xmit))
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break;
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writel(port->info->xmit.buf[port->info->xmit.tail], DANUBE_ASC1_TBUF);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static irqreturn_t
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danubeasc_tx_int (int irq, void *port)
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{
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writel(ASC_IRNCR_TIR, DANUBE_ASC1_IRNCR);
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danubeasc_start_tx(port);
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mask_and_ack_danube_irq(irq);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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danubeasc_er_int (int irq, void *port)
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{
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/* clear any pending interrupts */
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writel(readl(DANUBE_ASC1_WHBSTATE) | ASCWHBSTATE_CLRPE |
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ASCWHBSTATE_CLRFE | ASCWHBSTATE_CLRROE, DANUBE_ASC1_WHBSTATE);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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danubeasc_rx_int (int irq, void *port)
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{
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writel(ASC_IRNCR_RIR, DANUBE_ASC1_IRNCR);
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danubeasc_rx_chars((struct uart_port *) port);
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mask_and_ack_danube_irq(irq);
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return IRQ_HANDLED;
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}
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static unsigned int
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danubeasc_tx_empty (struct uart_port *port)
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{
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int status;
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status = readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK;
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return status ? 0 : TIOCSER_TEMT;
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}
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static unsigned int
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danubeasc_get_mctrl (struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
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}
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static void
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danubeasc_set_mctrl (struct uart_port *port, u_int mctrl)
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{
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return;
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}
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static void
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danubeasc_break_ctl (struct uart_port *port, int break_state)
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{
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return;
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}
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static void
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danubeasc1_hw_init (void)
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{
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/* this setup was probably already done in ROM/u-boot but we do it again*/
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/* TODO: GPIO pins are multifunction */
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writel(readl(DANUBE_ASC1_CLC) & ~DANUBE_ASC1_CLC_DISS, DANUBE_ASC1_CLC);
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writel((readl(DANUBE_ASC1_CLC) & ~ASCCLC_RMCMASK) | (1 << ASCCLC_RMCOFFSET), DANUBE_ASC1_CLC);
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writel(0, DANUBE_ASC1_PISEL);
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writel(((DANUBEASC_TXFIFO_FL << ASCTXFCON_TXFITLOFF) &
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ASCTXFCON_TXFITLMASK) | ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
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writel(((DANUBEASC_RXFIFO_FL << ASCRXFCON_RXFITLOFF) &
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ASCRXFCON_RXFITLMASK) | ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
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wmb ();
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/*framing, overrun, enable */
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writel(readl(DANUBE_ASC1_CON) | ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN,
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DANUBE_ASC1_CON);
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}
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static int
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danubeasc_startup (struct uart_port *port)
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{
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unsigned long flags;
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int retval;
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/* this assumes: CON.BRS = CON.FDE = 0 */
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if (uartclk == 0)
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uartclk = danube_get_fpi_hz();
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danubeasc_port.uartclk = uartclk;
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danubeasc1_hw_init();
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local_irq_save(flags);
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retval = request_irq(DANUBEASC1_RIR, danubeasc_rx_int, IRQF_DISABLED, "asc_rx", port);
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if (retval){
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printk("failed to request danubeasc_rx_int\n");
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return retval;
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}
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retval = request_irq(DANUBEASC1_TIR, danubeasc_tx_int, IRQF_DISABLED, "asc_tx", port);
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if (retval){
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printk("failed to request danubeasc_tx_int\n");
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goto err1;
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}
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retval = request_irq(DANUBEASC1_EIR, danubeasc_er_int, IRQF_DISABLED, "asc_er", port);
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if (retval){
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printk("failed to request danubeasc_er_int\n");
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goto err2;
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}
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writel(ASC_IRNREN_RX_BUF | ASC_IRNREN_TX_BUF | ASC_IRNREN_ERR | ASC_IRNREN_TX,
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DANUBE_ASC1_IRNREN);
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local_irq_restore(flags);
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return 0;
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err2:
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free_irq(DANUBEASC1_TIR, port);
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err1:
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free_irq(DANUBEASC1_RIR, port);
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local_irq_restore(flags);
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return retval;
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}
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static void
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danubeasc_shutdown (struct uart_port *port)
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{
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free_irq(DANUBEASC1_RIR, port);
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free_irq(DANUBEASC1_TIR, port);
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free_irq(DANUBEASC1_EIR, port);
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/*
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* disable the baudrate generator to disable the ASC
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*/
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writel(0, DANUBE_ASC1_CON);
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/* flush and then disable the fifos */
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writel(readl(DANUBE_ASC1_RXFCON) | ASCRXFCON_RXFFLU, DANUBE_ASC1_RXFCON);
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writel(readl(DANUBE_ASC1_RXFCON) & ~ASCRXFCON_RXFEN, DANUBE_ASC1_RXFCON);
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writel(readl(DANUBE_ASC1_TXFCON) | ASCTXFCON_TXFFLU, DANUBE_ASC1_TXFCON);
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writel(readl(DANUBE_ASC1_TXFCON) & ~ASCTXFCON_TXFEN, DANUBE_ASC1_TXFCON);
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}
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static void danubeasc_set_termios(struct uart_port *port, struct ktermios *new, struct ktermios *old)
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{
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unsigned int cflag;
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unsigned int iflag;
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unsigned int quot;
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unsigned int baud;
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unsigned int con = 0;
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unsigned long flags;
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cflag = new->c_cflag;
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iflag = new->c_iflag;
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/* byte size and parity */
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switch (cflag & CSIZE) {
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case CS7:
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con = ASCCON_M_7ASYNC;
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break;
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case CS5:
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case CS6:
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default:
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con = ASCCON_M_8ASYNC;
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break;
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}
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if (cflag & CSTOPB)
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con |= ASCCON_STP;
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if (cflag & PARENB) {
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if (!(cflag & PARODD))
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con &= ~ASCCON_ODD;
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else
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con |= ASCCON_ODD;
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}
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port->read_status_mask = ASCSTATE_ROE;
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if (iflag & INPCK)
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port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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port->ignore_status_mask = 0;
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if (iflag & IGNPAR)
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port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
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if (iflag & IGNBRK) {
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/*
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* If we're ignoring parity and break indicators,
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* ignore overruns too (for real raw support).
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*/
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if (iflag & IGNPAR)
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port->ignore_status_mask |= ASCSTATE_ROE;
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}
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if ((cflag & CREAD) == 0)
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port->ignore_status_mask |= UART_DUMMY_UER_RX;
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/* set error signals - framing, parity and overrun, enable receiver */
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con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
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local_irq_save(flags);
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/* set up CON */
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writel(readl(DANUBE_ASC1_CON) | con, DANUBE_ASC1_CON);
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/* Set baud rate - take a divider of 2 into account */
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baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
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quot = uart_get_divisor(port, baud);
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quot = quot / 2 - 1;
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/* disable the baudrate generator */
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writel(readl(DANUBE_ASC1_CON) & ~ASCCON_R, DANUBE_ASC1_CON);
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/* make sure the fractional divider is off */
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writel(readl(DANUBE_ASC1_CON) & ~ASCCON_FDE, DANUBE_ASC1_CON);
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/* set up to use divisor of 2 */
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writel(readl(DANUBE_ASC1_CON) & ~ASCCON_BRS, DANUBE_ASC1_CON);
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/* now we can write the new baudrate into the register */
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writel(quot, DANUBE_ASC1_BG);
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/* turn the baudrate generator back on */
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writel(readl(DANUBE_ASC1_CON) | ASCCON_R, DANUBE_ASC1_CON);
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/* enable rx */
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writel(ASCWHBSTATE_SETREN, DANUBE_ASC1_WHBSTATE);
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local_irq_restore(flags);
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}
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static const char*
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danubeasc_type (struct uart_port *port)
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{
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return port->type == PORT_DANUBEASC ? "DANUBEASC" : NULL;
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}
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static void
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danubeasc_release_port (struct uart_port *port)
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{
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return;
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}
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static int
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danubeasc_request_port (struct uart_port *port)
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{
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return 0;
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}
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static void
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danubeasc_config_port (struct uart_port *port, int flags)
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{
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if (flags & UART_CONFIG_TYPE) {
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port->type = PORT_DANUBEASC;
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danubeasc_request_port(port);
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}
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}
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static int
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danubeasc_verify_port (struct uart_port *port, struct serial_struct *ser)
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{
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int ret = 0;
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if (ser->type != PORT_UNKNOWN && ser->type != PORT_DANUBEASC)
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ret = -EINVAL;
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if (ser->irq < 0 || ser->irq >= NR_IRQS)
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ret = -EINVAL;
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if (ser->baud_base < 9600)
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ret = -EINVAL;
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return ret;
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}
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static struct uart_ops danubeasc_pops = {
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.tx_empty = danubeasc_tx_empty,
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.set_mctrl = danubeasc_set_mctrl,
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.get_mctrl = danubeasc_get_mctrl,
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.stop_tx = danubeasc_stop_tx,
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.start_tx = danubeasc_start_tx,
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.stop_rx = danubeasc_stop_rx,
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.enable_ms = danubeasc_enable_ms,
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.break_ctl = danubeasc_break_ctl,
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.startup = danubeasc_startup,
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.shutdown = danubeasc_shutdown,
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.set_termios = danubeasc_set_termios,
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.type = danubeasc_type,
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.release_port = danubeasc_release_port,
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.request_port = danubeasc_request_port,
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.config_port = danubeasc_config_port,
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.verify_port = danubeasc_verify_port,
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};
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static struct uart_port danubeasc_port = {
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membase: (void *)DANUBE_ASC1_BASE_ADDR,
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mapbase: DANUBE_ASC1_BASE_ADDR,
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iotype: SERIAL_IO_MEM,
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irq: DANUBEASC1_RIR,
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uartclk: 0,
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fifosize: 16,
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unused: {DANUBEASC1_TIR, DANUBEASC1_EIR},
|
|
type: PORT_DANUBEASC,
|
|
ops: &danubeasc_pops,
|
|
flags: ASYNC_BOOT_AUTOCONF,
|
|
};
|
|
|
|
static void
|
|
danubeasc_console_write (struct console *co, const char *s, u_int count)
|
|
{
|
|
int i, fifocnt;
|
|
unsigned long flags;
|
|
|
|
local_irq_save(flags);
|
|
for (i = 0; i < count; i++)
|
|
{
|
|
/* wait until the FIFO is not full */
|
|
do
|
|
{
|
|
fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
|
|
>> ASCFSTAT_TXFFLOFF;
|
|
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
|
|
|
|
if (s[i] == '\0')
|
|
{
|
|
break;
|
|
}
|
|
|
|
if (s[i] == '\n')
|
|
{
|
|
writel('\r', DANUBE_ASC1_TBUF);
|
|
do
|
|
{
|
|
fifocnt = (readl(DANUBE_ASC1_FSTAT) & ASCFSTAT_TXFFLMASK)
|
|
>> ASCFSTAT_TXFFLOFF;
|
|
} while (fifocnt == DANUBEASC_TXFIFO_FULL);
|
|
}
|
|
writel(s[i], DANUBE_ASC1_TBUF);
|
|
}
|
|
|
|
local_irq_restore(flags);
|
|
}
|
|
|
|
static int __init
|
|
danubeasc_console_setup (struct console *co, char *options)
|
|
{
|
|
struct uart_port *port;
|
|
int baud = 115200;
|
|
int bits = 8;
|
|
int parity = 'n';
|
|
int flow = 'n';
|
|
|
|
if (uartclk == 0)
|
|
uartclk = danube_get_fpi_hz();
|
|
co->index = 0;
|
|
port = &danubeasc_port;
|
|
danubeasc_port.uartclk = uartclk;
|
|
danubeasc_port.type = PORT_DANUBEASC;
|
|
|
|
if (options){
|
|
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
|
}
|
|
|
|
return uart_set_options(port, co, baud, parity, bits, flow);
|
|
}
|
|
|
|
static struct uart_driver danubeasc_reg;
|
|
static struct console danubeasc_console = {
|
|
name: "ttyS",
|
|
write: danubeasc_console_write,
|
|
device: uart_console_device,
|
|
setup: danubeasc_console_setup,
|
|
flags: CON_PRINTBUFFER,
|
|
index: -1,
|
|
data: &danubeasc_reg,
|
|
};
|
|
|
|
static int __init
|
|
danubeasc_console_init (void)
|
|
{
|
|
register_console(&danubeasc_console);
|
|
return 0;
|
|
}
|
|
console_initcall(danubeasc_console_init);
|
|
|
|
static struct uart_driver danubeasc_reg = {
|
|
.owner = THIS_MODULE,
|
|
.driver_name = "serial",
|
|
.dev_name = "ttyS",
|
|
.major = TTY_MAJOR,
|
|
.minor = 64,
|
|
.nr = 1,
|
|
.cons = &danubeasc_console,
|
|
};
|
|
|
|
static int __init
|
|
danubeasc_init (void)
|
|
{
|
|
unsigned char res;
|
|
|
|
uart_register_driver(&danubeasc_reg);
|
|
res = uart_add_one_port(&danubeasc_reg, &danubeasc_port);
|
|
|
|
return res;
|
|
}
|
|
|
|
static void __exit
|
|
danubeasc_exit (void)
|
|
{
|
|
uart_unregister_driver(&danubeasc_reg);
|
|
}
|
|
|
|
module_init(danubeasc_init);
|
|
module_exit(danubeasc_exit);
|
|
|
|
MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
|
|
MODULE_DESCRIPTION("MIPS Danube serial port driver");
|
|
MODULE_LICENSE("GPL");
|