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55be011a71
This backports GD SPI NAND support from nand/next to v5.10 Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
173 lines
5.7 KiB
Diff
173 lines
5.7 KiB
Diff
From bd568cc04c675b7fa97214d278a54794c2ecc2ad Mon Sep 17 00:00:00 2001
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From: Reto Schneider <reto.schneider@husqvarnagroup.com>
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Date: Thu, 11 Feb 2021 12:36:19 +0100
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Subject: [PATCH] mtd: spinand: gigadevice: Support GD5F1GQ5UExxG
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The relevant changes to the already existing GD5F1GQ4UExxG support has
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been determined by consulting the GigaDevice product change notice
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AN-0392-10, version 1.0 from November 30, 2020.
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As the overlaps are huge, variable names have been generalized
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accordingly.
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Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes),
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the new device ID, and the extra quad IO dummy byte, no changes had to
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be taken into account.
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New hardware features are not supported, namely:
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- Power on reset
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- Unique ID
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- Double transfer rate (DTR)
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- Parameter page
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- Random data quad IO
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The inverted semantic of the "driver strength" register bits, defaulting
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to 100% instead of 50% for the Q5 devices, got ignored as the driver has
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never touched them anyway.
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The no longer supported "read from cache during block erase"
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functionality is not reflected as the current SPI NAND core does not
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support it anyway.
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Implementation has been tested on MediaTek MT7688 based GARDENA smart
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Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
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Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
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Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
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Reviewed-by: Stefan Roese <sr@denx.de>
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Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch
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(cherry picked from commit 469b992489852b500d39048aa0013639dfe9f2e6)
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---
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drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++----
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1 file changed, 60 insertions(+), 9 deletions(-)
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--- a/drivers/mtd/nand/spi/gigadevice.c
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+++ b/drivers/mtd/nand/spi/gigadevice.c
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@@ -13,7 +13,10 @@
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#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4)
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#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4)
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-#define GD5FXGQ4UEXXG_REG_STATUS2 0xf0
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+#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS (1 << 4)
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+#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS (3 << 4)
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+
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+#define GD5FXGQXXEXXG_REG_STATUS2 0xf0
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#define GD5FXGQ4UXFXXG_STATUS_ECC_MASK (7 << 4)
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#define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS (0 << 4)
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@@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(str
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return -EINVAL;
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}
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-static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
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+static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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@@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_e
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return 0;
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}
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-static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
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+static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
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struct mtd_oob_region *region)
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{
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if (section)
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@@ -127,9 +130,10 @@ static int gd5fxgq4_variant2_ooblayout_f
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return 0;
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}
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-static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
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- .ecc = gd5fxgq4_variant2_ooblayout_ecc,
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- .free = gd5fxgq4_variant2_ooblayout_free,
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+/* Valid for Q4/Q5 and Q6 (untested) devices */
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+static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
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+ .ecc = gd5fxgqx_variant2_ooblayout_ecc,
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+ .free = gd5fxgqx_variant2_ooblayout_free,
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};
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static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
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@@ -165,7 +169,7 @@ static int gd5fxgq4uexxg_ecc_get_status(
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u8 status)
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{
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u8 status2;
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- struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
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+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
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&status2);
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int ret;
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@@ -203,6 +207,43 @@ static int gd5fxgq4uexxg_ecc_get_status(
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return -EINVAL;
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}
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+static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
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+ u8 status)
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+{
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+ u8 status2;
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+ struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
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+ &status2);
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+ int ret;
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+
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+ switch (status & STATUS_ECC_MASK) {
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+ case STATUS_ECC_NO_BITFLIPS:
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+ return 0;
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+
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+ case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
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+ /*
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+ * Read status2 register to determine a more fine grained
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+ * bit error status
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+ */
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+ ret = spi_mem_exec_op(spinand->spimem, &op);
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+ if (ret)
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+ return ret;
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+
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+ /*
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+ * 1 ... 4 bits are flipped (and corrected)
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+ */
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+ /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
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+ return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
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+
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+ case STATUS_ECC_UNCOR_ERROR:
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+ return -EBADMSG;
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+
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+ default:
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+ break;
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+ }
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+
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+ return -EINVAL;
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+}
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+
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static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
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u8 status)
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{
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@@ -282,7 +323,7 @@ static const struct spinand_info gigadev
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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- SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq4uexxg_ecc_get_status)),
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SPINAND_INFO("GD5F1GQ4UFxxG",
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SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
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@@ -292,8 +333,18 @@ static const struct spinand_info gigadev
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&write_cache_variants,
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&update_cache_variants),
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SPINAND_HAS_QE_BIT,
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- SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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gd5fxgq4ufxxg_ecc_get_status)),
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+ SPINAND_INFO("GD5F1GQ5UExxG",
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+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
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+ NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+ NAND_ECCREQ(4, 512),
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+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+ &write_cache_variants,
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+ &update_cache_variants),
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+ SPINAND_HAS_QE_BIT,
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+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
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+ gd5fxgq5xexxg_ecc_get_status)),
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};
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static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {
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