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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
136 lines
4.7 KiB
Diff
136 lines
4.7 KiB
Diff
From a67d1901741c162645eda0dbdc3a2c0c2aff5cf4 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Tue, 21 Dec 2021 14:49:36 +0100
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Subject: [PATCH] arm64: dts: ipq8074: Add WLAN node
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IPQ8074 has a AHB based Q6v5 802.11ax radios that are supported
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by the ath11k.
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Add the required DT node to enable the built-in radios.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 111 ++++++++++++++++++++++++++
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1 file changed, 111 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -998,6 +998,117 @@
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};
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};
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};
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+
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+ wifi: wifi@c0000000 {
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+ compatible = "qcom,ipq8074-wifi";
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+ reg = <0xc000000 0x2000000>;
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+
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+ interrupts = <GIC_SPI 320 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 319 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 316 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 315 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 314 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 302 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 301 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 293 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 292 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 291 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 290 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 289 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 288 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 239 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 234 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 233 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 232 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 231 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 230 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 224 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 223 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 183 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 180 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 179 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 176 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 163 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 160 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 159 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>,
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+ <GIC_SPI 156 IRQ_TYPE_EDGE_RISING>;
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+
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+ interrupt-names = "misc-pulse1",
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+ "misc-latch",
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+ "sw-exception",
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+ "ce0",
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+ "ce1",
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+ "ce2",
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+ "ce3",
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+ "ce4",
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+ "ce5",
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+ "ce6",
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+ "ce7",
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+ "ce8",
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+ "ce9",
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+ "ce10",
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+ "ce11",
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+ "host2wbm-desc-feed",
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+ "host2reo-re-injection",
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+ "host2reo-command",
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+ "host2rxdma-monitor-ring3",
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+ "host2rxdma-monitor-ring2",
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+ "host2rxdma-monitor-ring1",
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+ "reo2ost-exception",
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+ "wbm2host-rx-release",
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+ "reo2host-status",
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+ "reo2host-destination-ring4",
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+ "reo2host-destination-ring3",
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+ "reo2host-destination-ring2",
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+ "reo2host-destination-ring1",
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+ "rxdma2host-monitor-destination-mac3",
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+ "rxdma2host-monitor-destination-mac2",
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+ "rxdma2host-monitor-destination-mac1",
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+ "ppdu-end-interrupts-mac3",
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+ "ppdu-end-interrupts-mac2",
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+ "ppdu-end-interrupts-mac1",
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+ "rxdma2host-monitor-status-ring-mac3",
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+ "rxdma2host-monitor-status-ring-mac2",
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+ "rxdma2host-monitor-status-ring-mac1",
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+ "host2rxdma-host-buf-ring-mac3",
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+ "host2rxdma-host-buf-ring-mac2",
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+ "host2rxdma-host-buf-ring-mac1",
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+ "rxdma2host-destination-ring-mac3",
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+ "rxdma2host-destination-ring-mac2",
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+ "rxdma2host-destination-ring-mac1",
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+ "host2tcl-input-ring4",
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+ "host2tcl-input-ring3",
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+ "host2tcl-input-ring2",
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+ "host2tcl-input-ring1",
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+ "wbm2host-tx-completions-ring3",
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+ "wbm2host-tx-completions-ring2",
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+ "wbm2host-tx-completions-ring1",
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+ "tcl2host-status-ring";
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+ qcom,rproc = <&q6v5_wcss>;
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+ status = "disabled";
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+ };
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};
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timer {
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