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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
121 lines
2.9 KiB
Diff
121 lines
2.9 KiB
Diff
From 7388400b8bd42f71d040dbf2fdbdcb834fcc0ede Mon Sep 17 00:00:00 2001
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From: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Date: Sat, 30 Jan 2021 10:50:13 +0530
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Subject: [PATCH] arm64: dts: qcom: Enable Q6v5 WCSS for ipq8074 SoC
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Enable remoteproc WCSS PIL driver with glink and ssr subdevices.
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Also enables smp2p and mailboxes required for IPC.
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Signed-off-by: Gokul Sriram Palanisamy <gokulsri@codeaurora.org>
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Signed-off-by: Sricharan R <sricharan@codeaurora.org>
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Signed-off-by: Nikhil Prakash V <nprakash@codeaurora.org>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 81 +++++++++++++++++++++++++++
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1 file changed, 81 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -140,6 +140,32 @@
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};
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};
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+ wcss: smp2p-wcss {
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+ compatible = "qcom,smp2p";
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+ qcom,smem = <435>, <428>;
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+
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+ interrupt-parent = <&intc>;
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+ interrupts = <0 322 1>;
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+
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+ mboxes = <&apcs_glb 9>;
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+
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+ qcom,local-pid = <0>;
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+ qcom,remote-pid = <1>;
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+
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+ wcss_smp2p_out: master-kernel {
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+ qcom,entry-name = "master-kernel";
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+ qcom,smp2p-feature-ssr-ack;
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+ #qcom,smem-state-cells = <1>;
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+ };
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+
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+ wcss_smp2p_in: slave-kernel {
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+ qcom,entry-name = "slave-kernel";
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+
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+ interrupt-controller;
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+ #interrupt-cells = <2>;
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+ };
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+ };
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+
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soc: soc {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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@@ -409,6 +435,11 @@
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#hwlock-cells = <1>;
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};
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+ tcsr_q6: syscon@1945000 {
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+ compatible = "syscon";
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+ reg = <0x01945000 0xe000>;
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+ };
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+
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spmi_bus: spmi@200f000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x0200f000 0x001000>,
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@@ -917,6 +948,56 @@
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"axi_s_sticky";
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status = "disabled";
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};
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+
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+ q6v5_wcss: q6v5_wcss@cd00000 {
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+ compatible = "qcom,ipq8074-wcss-pil";
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+ reg = <0x0cd00000 0x4040>,
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+ <0x004ab000 0x20>;
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+ reg-names = "qdsp6",
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+ "rmb";
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+ qca,auto-restart;
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+ qca,extended-intc;
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+ interrupts-extended = <&intc 0 325 1>,
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+ <&wcss_smp2p_in 0 0>,
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+ <&wcss_smp2p_in 1 0>,
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+ <&wcss_smp2p_in 2 0>,
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+ <&wcss_smp2p_in 3 0>;
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+ interrupt-names = "wdog",
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+ "fatal",
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+ "ready",
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+ "handover",
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+ "stop-ack";
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+
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+ resets = <&gcc GCC_WCSSAON_RESET>,
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+ <&gcc GCC_WCSS_BCR>,
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+ <&gcc GCC_WCSS_Q6_BCR>;
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+
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+ reset-names = "wcss_aon_reset",
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+ "wcss_reset",
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+ "wcss_q6_reset";
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+
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+ clocks = <&gcc GCC_PRNG_AHB_CLK>;
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+ clock-names = "prng";
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+
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+ qcom,halt-regs = <&tcsr_q6 0xa000 0xd000 0x0>;
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+
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+ qcom,smem-states = <&wcss_smp2p_out 0>,
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+ <&wcss_smp2p_out 1>;
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+ qcom,smem-state-names = "shutdown",
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+ "stop";
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+
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+ memory-region = <&q6_region>;
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+
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+ glink-edge {
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+ interrupts = <GIC_SPI 321 IRQ_TYPE_EDGE_RISING>;
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+ qcom,remote-pid = <1>;
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+ mboxes = <&apcs_glb 8>;
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+
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+ rpm_requests {
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+ qcom,glink-channels = "IPCRTR";
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+ };
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+ };
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+ };
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};
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timer {
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