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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
98 lines
3.0 KiB
Diff
98 lines
3.0 KiB
Diff
From 625c90a8266e432ea15e109123ca941062b63f76 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:48:40 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node
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IPQ8074 comes in 2 silicon versions:
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* v1 with 2x Gen2 PCIe ports and QMP PHY-s
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* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s
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v2 is the final and production version that is actually supported by the
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kernel, however it looks like PCIe related nodes were added for the v1 SoC.
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Finish the PCIe fixup by using the correct compatible, adding missing ATU
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register space, declaring max-link-speed, use correct ranges, add missing
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clocks and resets.
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Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 30 +++++++++++++++------------
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1 file changed, 17 insertions(+), 13 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -854,16 +854,18 @@
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};
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pcie0: pci@20000000 {
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- compatible = "qcom,pcie-ipq8074";
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+ compatible = "qcom,pcie-ipq8074-gen3";
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reg = <0x20000000 0xf1d>,
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<0x20000f20 0xa8>,
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- <0x00080000 0x2000>,
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+ <0x20001000 0x1000>,
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+ <0x00080000 0x4000>,
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<0x20100000 0x1000>;
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- reg-names = "dbi", "elbi", "parf", "config";
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+ reg-names = "dbi", "elbi", "atu", "parf", "config";
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device_type = "pci";
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linux,pci-domain = <0>;
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bus-range = <0x00 0xff>;
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num-lanes = <1>;
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+ max-link-speed = <3>;
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#address-cells = <3>;
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#size-cells = <2>;
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@@ -871,9 +873,9 @@
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x20200000 0x20200000
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- 0 0x100000 /* downstream I/O */
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- 0x82000000 0 0x20300000 0x20300000
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- 0 0xd00000>; /* non-prefetchable memory */
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+ 0 0x10000>, /* downstream I/O */
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+ <0x82000000 0 0x20220000 0x20220000
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+ 0 0xfde0000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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@@ -891,28 +893,30 @@
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clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
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<&gcc GCC_PCIE0_AXI_M_CLK>,
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<&gcc GCC_PCIE0_AXI_S_CLK>,
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- <&gcc GCC_PCIE0_AHB_CLK>,
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- <&gcc GCC_PCIE0_AUX_CLK>;
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-
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+ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>,
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+ <&gcc GCC_PCIE0_RCHNG_CLK>;
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clock-names = "iface",
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"axi_m",
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"axi_s",
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- "ahb",
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- "aux";
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+ "axi_bridge",
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+ "rchng";
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+
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resets = <&gcc GCC_PCIE0_PIPE_ARES>,
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<&gcc GCC_PCIE0_SLEEP_ARES>,
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<&gcc GCC_PCIE0_CORE_STICKY_ARES>,
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<&gcc GCC_PCIE0_AXI_MASTER_ARES>,
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<&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
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<&gcc GCC_PCIE0_AHB_ARES>,
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- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
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+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>,
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+ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>;
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reset-names = "pipe",
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"sleep",
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"sticky",
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"axi_m",
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"axi_s",
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"ahb",
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- "axi_m_sticky";
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+ "axi_m_sticky",
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+ "axi_s_sticky";
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status = "disabled";
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};
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};
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