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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
135 lines
4.2 KiB
Diff
135 lines
4.2 KiB
Diff
From e593e834fe8ba9bf314d8215ac05d8787f81efda Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Fri, 19 Aug 2022 00:02:42 +0200
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Subject: [PATCH] thermal/drivers/tsens: Add support for combined interrupt
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Despite using tsens v2.3 IP, IPQ8074 and IPQ6018 only have one IRQ for
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signaling both up/low and critical trips.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20220818220245.338396-2-robimarko@gmail.com
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Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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---
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drivers/thermal/qcom/tsens-8960.c | 1 +
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drivers/thermal/qcom/tsens-v0_1.c | 1 +
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drivers/thermal/qcom/tsens-v1.c | 1 +
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drivers/thermal/qcom/tsens-v2.c | 1 +
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drivers/thermal/qcom/tsens.c | 38 ++++++++++++++++++++++++++-----
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drivers/thermal/qcom/tsens.h | 2 ++
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6 files changed, 38 insertions(+), 6 deletions(-)
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--- a/drivers/thermal/qcom/tsens-8960.c
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+++ b/drivers/thermal/qcom/tsens-8960.c
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@@ -269,6 +269,7 @@ static const struct tsens_ops ops_8960 =
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static struct tsens_features tsens_8960_feat = {
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.ver_major = VER_0,
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.crit_int = 0,
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+ .combo_int = 0,
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.adc = 1,
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.srot_split = 0,
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.max_sensors = 11,
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--- a/drivers/thermal/qcom/tsens-v0_1.c
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+++ b/drivers/thermal/qcom/tsens-v0_1.c
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@@ -539,6 +539,7 @@ static int calibrate_9607(struct tsens_p
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static struct tsens_features tsens_v0_1_feat = {
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.ver_major = VER_0_1,
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.crit_int = 0,
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+ .combo_int = 0,
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.adc = 1,
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.srot_split = 1,
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.max_sensors = 11,
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--- a/drivers/thermal/qcom/tsens-v1.c
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+++ b/drivers/thermal/qcom/tsens-v1.c
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@@ -302,6 +302,7 @@ static int calibrate_8976(struct tsens_p
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static struct tsens_features tsens_v1_feat = {
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.ver_major = VER_1_X,
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.crit_int = 0,
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+ .combo_int = 0,
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.adc = 1,
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.srot_split = 1,
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.max_sensors = 11,
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--- a/drivers/thermal/qcom/tsens-v2.c
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+++ b/drivers/thermal/qcom/tsens-v2.c
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@@ -31,6 +31,7 @@
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static struct tsens_features tsens_v2_feat = {
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.ver_major = VER_2_X,
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.crit_int = 1,
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+ .combo_int = 0,
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.adc = 0,
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.srot_split = 1,
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.max_sensors = 16,
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--- a/drivers/thermal/qcom/tsens.c
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+++ b/drivers/thermal/qcom/tsens.c
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@@ -531,6 +531,27 @@ static irqreturn_t tsens_irq_thread(int
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return IRQ_HANDLED;
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}
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+/**
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+ * tsens_combined_irq_thread() - Threaded interrupt handler for combined interrupts
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+ * @irq: irq number
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+ * @data: tsens controller private data
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+ *
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+ * Handle the combined interrupt as if it were 2 separate interrupts, so call the
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+ * critical handler first and then the up/low one.
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+ *
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+ * Return: IRQ_HANDLED
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+ */
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+static irqreturn_t tsens_combined_irq_thread(int irq, void *data)
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+{
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+ irqreturn_t ret;
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+
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+ ret = tsens_critical_irq_thread(irq, data);
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+ if (ret != IRQ_HANDLED)
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+ return ret;
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+
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+ return tsens_irq_thread(irq, data);
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+}
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+
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static int tsens_set_trips(void *_sensor, int low, int high)
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{
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struct tsens_sensor *s = _sensor;
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@@ -1075,13 +1096,18 @@ static int tsens_register(struct tsens_p
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tsens_mC_to_hw(priv->sensor, 0));
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}
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- ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
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- if (ret < 0)
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- return ret;
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+ if (priv->feat->combo_int) {
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+ ret = tsens_register_irq(priv, "combined",
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+ tsens_combined_irq_thread);
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+ } else {
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+ ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
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+ if (ret < 0)
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+ return ret;
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- if (priv->feat->crit_int)
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- ret = tsens_register_irq(priv, "critical",
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- tsens_critical_irq_thread);
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+ if (priv->feat->crit_int)
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+ ret = tsens_register_irq(priv, "critical",
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+ tsens_critical_irq_thread);
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+ }
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return ret;
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}
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--- a/drivers/thermal/qcom/tsens.h
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+++ b/drivers/thermal/qcom/tsens.h
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@@ -495,6 +495,7 @@ enum regfield_ids {
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* struct tsens_features - Features supported by the IP
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* @ver_major: Major number of IP version
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* @crit_int: does the IP support critical interrupts?
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+ * @combo_int: does the IP use one IRQ for up, low and critical thresholds?
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* @adc: do the sensors only output adc code (instead of temperature)?
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* @srot_split: does the IP neatly splits the register space into SROT and TM,
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* with SROT only being available to secure boot firmware?
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@@ -504,6 +505,7 @@ enum regfield_ids {
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struct tsens_features {
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unsigned int ver_major;
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unsigned int crit_int:1;
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+ unsigned int combo_int:1;
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unsigned int adc:1;
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unsigned int srot_split:1;
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unsigned int has_watchdog:1;
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