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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
28 lines
1.0 KiB
Diff
28 lines
1.0 KiB
Diff
From 8e6af077ced3931ac18e37f0eb3fc6f1a20b0e4a Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Mon, 4 Jul 2022 16:35:54 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq8074: add reset to SDHCI
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Add reset to SDHCI controller so it can be reset to avoid timeout issues
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after software reset due to bootloader set configuration.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
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Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20220704143554.1180927-2-robimarko@gmail.com
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -389,6 +389,7 @@
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<&gcc GCC_SDCC1_APPS_CLK>,
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<&xo>;
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clock-names = "iface", "core", "xo";
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+ resets = <&gcc GCC_SDCC1_BCR>;
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max-frequency = <384000000>;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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