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9a26a9e8b9
The device tree files are now matching the kernel 4.17 and this will be send also for integration into mainline U-Boot. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
64 lines
1.9 KiB
Diff
64 lines
1.9 KiB
Diff
From 96c04aab58e351fa9ed7e95783018d6dbf60768f Mon Sep 17 00:00:00 2001
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From: Jun Nie <jun.nie@linaro.org>
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Date: Mon, 7 May 2018 13:03:40 +0530
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Subject: sunxi: h3: Sync OTG and HCI nodes from Linux DT
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Allwinner H3 have a dual-routed USB PHY0 -- routed to either OHCI/EHCI
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or MUSB controller.
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Signed-off-by: Jun Nie <jun.nie@linaro.org>
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Reviewed-by: Jagan Teki <jagan@openedev.com>
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Acked-by: Jun Nie <jun.nie@linaro.org>
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---
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arch/arm/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
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1 file changed, 32 insertions(+)
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--- a/arch/arm/dts/sun8i-h3.dtsi
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+++ b/arch/arm/dts/sun8i-h3.dtsi
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@@ -219,6 +219,19 @@
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#size-cells = <0>;
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};
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+ usb_otg: usb@1c19000 {
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+ compatible = "allwinner,sun8i-h3-musb";
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+ reg = <0x01c19000 0x400>;
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+ clocks = <&ccu CLK_BUS_OTG>;
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+ resets = <&ccu RST_BUS_OTG>;
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+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "mc";
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+ phys = <&usbphy 0>;
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+ phy-names = "usb";
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+ extcon = <&usbphy 0>;
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+ status = "disabled";
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+ };
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+
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usbphy: phy@01c19400 {
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compatible = "allwinner,sun8i-h3-usb-phy";
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reg = <0x01c19400 0x2c>,
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@@ -251,6 +264,25 @@
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#phy-cells = <1>;
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};
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+ ehci0: usb@1c1a000 {
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+ compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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+ reg = <0x01c1a000 0x100>;
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+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
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+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
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+ status = "disabled";
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+ };
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+
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+ ohci0: usb@1c1a400 {
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+ compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
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+ reg = <0x01c1a400 0x100>;
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+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
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+ clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
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+ <&ccu CLK_USB_OHCI0>;
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+ resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
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+ status = "disabled";
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+ };
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+
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ehci1: usb@01c1b000 {
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compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
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reg = <0x01c1b000 0x100>;
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