mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-27 01:11:14 +00:00
b92ec82235
Removed upstreamed: generic/backport-5.10/350-v5.18-MIPS-pgalloc-fix-memory-leak-caused-by-pgd_free.patch generic/pending-5.10/850-0014-PCI-aardvark-Fix-reading-PCI_EXP_RTSTA_PME-bit-on-em.patch ipq40xx/patches-5.10/105-ipq40xx-fix-sleep-clock.patch All patches automatically rebased. Build system: x86_64 Build-tested: bcm2711/RPi4B, mt7622/RT3200 Run-tested: bcm2711/RPi4B, mt7622/RT3200 Compile-/run-tested: ath79/generic (Archer C7 v2). Signed-off-by: John Audia <graysky@archlinux.us>
100 lines
2.9 KiB
Diff
100 lines
2.9 KiB
Diff
From b8afc254b40167fd37b4d4263e750dab1f9ef157 Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <john@phrozen.org>
|
|
Date: Wed, 9 Sep 2020 18:38:31 +0200
|
|
Subject: [PATCH] ARM: dts: qcom: ipq4019: add USB devicetree nodes
|
|
|
|
Since we now have driver for the USB PHY, and USB controller is already supported by the DWC3 driver lets add the necessary nodes to DTSI.
|
|
|
|
Signed-off-by: John Crispin <john@phrozen.org>
|
|
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
|
|
Cc: Luka Perkov <luka.perkov@sartura.hr>
|
|
Reviewed-by: Vinod Koul <vkoul@kernel.org>
|
|
Link: https://lore.kernel.org/r/20200909163831.1894142-1-robert.marko@sartura.hr
|
|
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
|
|
---
|
|
arch/arm/boot/dts/qcom-ipq4019.dtsi | 74 +++++++++++++++++++++++++++++
|
|
1 file changed, 74 insertions(+)
|
|
|
|
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
|
|
@@ -606,5 +606,79 @@
|
|
reg = <4>;
|
|
};
|
|
};
|
|
+
|
|
+ usb3_ss_phy: ssphy@9a000 {
|
|
+ compatible = "qcom,usb-ss-ipq4019-phy";
|
|
+ #phy-cells = <0>;
|
|
+ reg = <0x9a000 0x800>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB3_UNIPHY_PHY_ARES>;
|
|
+ reset-names = "por_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb3_hs_phy: hsphy@a6000 {
|
|
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
|
+ #phy-cells = <0>;
|
|
+ reg = <0xa6000 0x40>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB3_HSPHY_POR_ARES>, <&gcc USB3_HSPHY_S_ARES>;
|
|
+ reset-names = "por_rst", "srif_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb3: usb3@8af8800 {
|
|
+ compatible = "qcom,dwc3";
|
|
+ reg = <0x8af8800 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc GCC_USB3_MASTER_CLK>,
|
|
+ <&gcc GCC_USB3_SLEEP_CLK>,
|
|
+ <&gcc GCC_USB3_MOCK_UTMI_CLK>;
|
|
+ clock-names = "master", "sleep", "mock_utmi";
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@8a00000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x8a00000 0xf8000>;
|
|
+ interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ phys = <&usb3_hs_phy>, <&usb3_ss_phy>;
|
|
+ phy-names = "usb2-phy", "usb3-phy";
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
+
|
|
+ usb2_hs_phy: hsphy@a8000 {
|
|
+ compatible = "qcom,usb-hs-ipq4019-phy";
|
|
+ #phy-cells = <0>;
|
|
+ reg = <0xa8000 0x40>;
|
|
+ reg-names = "phy_base";
|
|
+ resets = <&gcc USB2_HSPHY_POR_ARES>, <&gcc USB2_HSPHY_S_ARES>;
|
|
+ reset-names = "por_rst", "srif_rst";
|
|
+ status = "disabled";
|
|
+ };
|
|
+
|
|
+ usb2: usb2@60f8800 {
|
|
+ compatible = "qcom,dwc3";
|
|
+ reg = <0x60f8800 0x100>;
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <1>;
|
|
+ clocks = <&gcc GCC_USB2_MASTER_CLK>,
|
|
+ <&gcc GCC_USB2_SLEEP_CLK>,
|
|
+ <&gcc GCC_USB2_MOCK_UTMI_CLK>;
|
|
+ clock-names = "master", "sleep", "mock_utmi";
|
|
+ ranges;
|
|
+ status = "disabled";
|
|
+
|
|
+ dwc3@6000000 {
|
|
+ compatible = "snps,dwc3";
|
|
+ reg = <0x6000000 0xf8000>;
|
|
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ phys = <&usb2_hs_phy>;
|
|
+ phy-names = "usb2-phy";
|
|
+ dr_mode = "host";
|
|
+ };
|
|
+ };
|
|
};
|
|
};
|