openwrt/target/linux/ath79/dts/qca9550_airtight_c-75.dts
Adrian Schmutzler 7054721cf9 ath79: enable UART in SoC DTSI files
The uart node is enabled on all devices except one (GL-USB150 *).
Thus, let's not have a few hundred nodes to enable it, but do not
disable it in the first place.

Where the majority of devices is using it, also move the serial0
alias to the DTSI.

*) Since GL-USB150 even defines serial0 alias, the missing uart
   is probably just a mistake. Anyway, disable it for now so this
   patch stays cosmetic.

Apply this to 21.02 as well to remove an unnecessary backporting
pitfall.

Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
(cherry picked from commit 3a4b751110)
2021-02-25 14:42:11 +01:00

182 lines
2.9 KiB
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// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
#include "qca955x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
/ {
model = "AirTight Networks C-75";
compatible = "airtight,c-75", "qca,qca9550", "qca,qca9558";
aliases {
label-mac-device = &eth0;
led-boot = &led_power;
led-failsafe = &led_power;
led-upgrade = &led_power;
};
keys {
compatible = "gpio-keys";
reset {
label = "reset";
linux,code = <KEY_RESTART>;
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
};
};
leds {
compatible = "gpio-leds";
led_power: power {
label = "amber:power";
gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
wlan2g {
label = "green:wlan2g";
gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
linux,default-trigger = "phy1tpt";
};
};
virtual_flash {
compatible = "mtd-concat";
devices = <&fwconcat0 &fwconcat1>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "firmware";
reg = <0x0 0x1f90000>;
compatible = "denx,uimage";
};
};
};
};
&eth0 {
status = "okay";
mtd-mac-address = <&art 0x0>;
phy-handle = <&phy0>;
pll-data = <0xa6000000 0x00000101 0x00001616>;
};
&mdio0 {
status = "okay";
phy0: ethernet-phy@0 {
reg = <0>;
qca,ar8327-initvals = <
0x04 0x07600000 /* PORT0 PAD MODE CTRL */
0x0c 0x00080080 /* PORT6 PAD MODE CTRL */
0x58 0xc935c935 /* LED2 CTRL */
0x5c 0x03ffff00 /* LED3 CTRL */
0x7c 0x0000007e /* PORT0_STATUS */
0x94 0x0000007e /* PORT6_STATUS */
>;
};
};
&eth1 {
status = "okay";
mtd-mac-address = <&art 0x6>;
pll-data = <0x03000101 0x00000101 0x00001616>;
fixed-link {
speed = <1000>;
full-duplex;
};
};
&pcie0 {
status = "okay";
wifi@0,0 {
compatible = "qcom,ath10k";
reg = <0x0000 0 0 0 0>;
};
};
&spi {
status = "okay";
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "u-boot";
reg = <0x000000 0x040000>;
read-only;
};
partition@40000 {
label = "u-boot-env";
reg = <0x040000 0x010000>;
};
partition@50000 {
label = "wlandrv";
reg = <0x050000 0x010000>;
read-only;
};
fwconcat0: partition@60000 {
label = "fwconcat0";
reg = <0x060000 0xf90000>;
};
art: partition@ff0000 {
label = "art";
reg = <0xff0000 0x010000>;
read-only;
};
};
};
flash@1 {
compatible = "jedec,spi-nor";
reg = <1>;
spi-max-frequency = <25000000>;
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
fwconcat1: partition@0 {
label = "fwconcat1";
reg = <0x0 0x1000000>;
};
};
};
};
&usb_phy0 {
status = "okay";
};
&usb0 {
status = "okay";
};
&wmac {
status = "okay";
mtd-cal-data = <&art 0x1000>;
};