mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
b4aad29a1d
Enable testing kernel. Delete upstreamed patches: 0098-disable_cm.patch can be dropped, upstream fixed CM handling. Fix compile errors by using new kernel APIs. Fix fuzz by manually editing patches to ensure the code goes in the right place. For 721-NET-no-auto-carrier-off-support.patch, revert upstream commit a307593a6 to keep the OpenWrt ralink driver operational. Add mt7621-pci-phy patch to select REGMAP_MMIO as discussed in PR #3693 and #3952. Rename patches to follow the 3-digit classification from the OpenWrt Developer Guide. Run automatic quilt refresh. Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
22 lines
704 B
Diff
22 lines
704 B
Diff
--- a/arch/mips/pci/pci-mt7620.c
|
|
+++ b/arch/mips/pci/pci-mt7620.c
|
|
@@ -32,6 +32,7 @@
|
|
#define PPLL_CFG1 0x9c
|
|
|
|
#define PPLL_DRV 0xa0
|
|
+#define PPLL_LD BIT(23)
|
|
#define PDRV_SW_SET BIT(31)
|
|
#define LC_CKDRVPD BIT(19)
|
|
#define LC_CKDRVOHZ BIT(18)
|
|
@@ -239,8 +240,8 @@ static int mt7620_pci_hw_init(struct pla
|
|
rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
|
|
mdelay(100);
|
|
|
|
- if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
|
|
- dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
|
|
+ if (!(rt_sysc_r32(PPLL_CFG1) & PPLL_LD)) {
|
|
+ dev_err(&pdev->dev, "MT7620 PPLL is unlocked, aborting init\n");
|
|
reset_control_assert(rstpcie0);
|
|
rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
|
|
return -1;
|