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01d8e41c16
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.51 Removed upstreamed: generic/backport-6.6/200-regmap-maple-work-around-false-positive-warning.patch generic/backport-6.6/822-v6.11-0012-nvmem-Fix-return-type-of-devm_nvmem_device_get-in-ke.patch bcm27xx/patches-6.6/950-1018-drivers-mmc-apply-SD-quirks-earlier-during-probe.patch Manually rebased: bcm27xx/patches-6.6/950-0993-drivers-mmc-cqhci-clear-CQHCI_CTL-if-halt-fails.patch ramips/patches-6.6/311-MIPS-use-set_mode-to-enable-disable-the-cevt-r4k-irq.patch[4] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=e42ea96d6d36a16526cb82b8aa2e5422814c3250 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=3d1baf322a3a69b38b6b2d511cfe0d611d1b5462 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.51&id=115a755bb38db5a1175be44e6a9a93a0a8233885 4. Adapted the changes from Hauke Mehrtens' modification in PR#16366 to 5.15.167 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me> Link: https://github.com/openwrt/openwrt/pull/16370 Signed-off-by: Robert Marko <robimarko@gmail.com>
117 lines
2.9 KiB
Diff
117 lines
2.9 KiB
Diff
From d3cf2859a056273400fbdf9d389b75750ff6ca5e Mon Sep 17 00:00:00 2001
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From: David Abdurachmanov <david.abdurachmanov@sifive.com>
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Date: Fri, 14 May 2021 05:27:51 -0700
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Subject: [PATCH 6/7] riscv: sifive: unleashed: define opp table (cpufreq)
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Source: https://github.com/sifive/riscv-linux/commits/dev/paulw/cpufreq-dt-aloe-v5.3-rc4
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Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
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---
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arch/riscv/Kconfig | 8 +++++
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arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 5 ++++
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.../riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 34 ++++++++++++++++++++++
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3 files changed, 47 insertions(+)
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--- a/arch/riscv/Kconfig
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+++ b/arch/riscv/Kconfig
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@@ -897,6 +897,14 @@ config PORTABLE
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select MMU
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select OF
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+menu "CPU Power Management"
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+
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+source "drivers/cpuidle/Kconfig"
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+
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+source "drivers/cpufreq/Kconfig"
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+
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+endmenu
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+
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menu "Power management options"
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source "kernel/power/Kconfig"
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--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
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@@ -30,6 +30,7 @@
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i-cache-size = <16384>;
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reg = <0>;
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riscv,isa = "rv64imac";
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+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
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status = "disabled";
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -54,6 +55,7 @@
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reg = <1>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -78,6 +80,7 @@
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reg = <2>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu2_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -102,6 +105,7 @@
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reg = <3>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu3_intc: interrupt-controller {
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#interrupt-cells = <1>;
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@@ -126,6 +130,7 @@
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reg = <4>;
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riscv,isa = "rv64imafdc";
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tlb-split;
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+ clocks = <&prci FU540_PRCI_CLK_COREPLL>;
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next-level-cache = <&l2cache>;
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cpu4_intc: interrupt-controller {
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#interrupt-cells = <1>;
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--- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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+++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts
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@@ -80,6 +80,40 @@
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label = "d4";
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};
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};
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+
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+ fu540_c000_opp_table: opp-table {
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+ compatible = "operating-points-v2";
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+ opp-shared;
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+
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+ opp-350000000 {
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+ opp-hz = /bits/ 64 <350000000>;
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+ };
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+ opp-700000000 {
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+ opp-hz = /bits/ 64 <700000000>;
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+ };
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+ opp-999999999 {
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+ opp-hz = /bits/ 64 <999999999>;
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+ };
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+ opp-1400000000 {
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+ opp-hz = /bits/ 64 <1400000000>;
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+ };
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+ };
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+};
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+
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+&cpu0 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu1 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu2 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu3 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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+};
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+&cpu4 {
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+ operating-points-v2 = <&fu540_c000_opp_table>;
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};
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&uart0 {
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