mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
d6d8851d12
Manually rebased:
bcm27xx/patches-5.15/950-0421-Support-RPi-DPI-interface-in-mode6-for-18-bit-color.patch
bcm27xx/patches-5.15/950-0706-media-i2c-imx219-Scale-the-pixel-clock-rate-for-the-.patch
ramips/patches-5.15/810-uvc-add-iPassion-iP2970-support.patch
Removed upstreamed:
bcm27xx/patches-5.15/950-0707-drm-vc4-For-DPI-MEDIA_BUS_FMT_RGB565_1X16-is-mode-1-.patch[1]
bcm27xx/patches-5.15/950-0596-drm-vc4-dpi-Add-option-for-inverting-pixel-clock-and.patch[2]
ipq807x/0006-v5.16-arm64-dts-qcom-Fix-IPQ8074-PCIe-PHY-nodes.patch [3]
ipq807x/0034-v6.1-arm64-dts-qcom-ipq8074-fix-PCIe-PHY-serdes-size.patch [4]
ipq807x/0103-arm64-dts-qcom-ipq8074-fix-Gen2-PCIe-QMP-PHY.patch [5]
ipq807x/0104-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-QMP-PHY.patch [6]
ipq807x/0105-arm64-dts-qcom-ipq8074-correct-Gen2-PCIe-ranges.patch [7]
ipq807x/0108-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-node.patch [8]
ipq807x/0109-arm64-dts-qcom-ipq8074-correct-PCIe-QMP-PHY-output-c.patch [9]
ipq807x/0132-arm64-dts-qcom-ipq8074-correct-USB3-QMP-PHY-s-clock-.patch [10]
All other patches automatically rebased.
1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.99&id=d2991e6b30020e286f2dd9d3b4f43548c547caa6
2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/drivers/gpu/drm/vc4/vc4_dpi.c?h=v5.15.100&id=8e04aaffb6de5f1ae61de7b671c1531172ccf429
3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=a55a645aa303a3f7ec37db69822d5420657626da
4. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=d9df682bcea57fa25f37bbf17eae56fa05662635
5. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=7e6eeb5fb3aa9e5feffdb6e137dcc06f5f6410e1
6. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=e88204931d9a60634cd50bbc679f045439c4b91d
7. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=1563af0f28afd3b6d64ac79a2aecced3969c90bf
8. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=feb8c71f015d416f1afe90e1f62cf51e47376c67
9. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=69c7a270357a7d50ffd3471b14c60250041200e3
10. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/arch/arm64/boot/dts/qcom/ipq8074.dtsi?h=v5.15.99&id=dd3d021ae5471d98adf81f1e897431c8657d0a18
Build system: x86_64
Build-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3
Run-tested: bcm2711/RPi4B, ramips/tplink_archer-a6-v3
Signed-off-by: John Audia <therealgraysky@proton.me>
Tested-by: Robert Marko <robimarko@gmail.com> #ipq807x/Dynalink WRX36
Tested-by: Stefan Lippers-Hollmann <s.l-h@gmx.de> #ipq807x/ax3600, x86_64/FW-7543B, ath79/tl-wdr3600, ipq806x/g10, ipq806x/nbg6817
333 lines
9.3 KiB
Diff
333 lines
9.3 KiB
Diff
From: Chuanjia Liu <chuanjia.liu@mediatek.com>
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Date: Mon, 23 Aug 2021 11:27:59 +0800
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Subject: [PATCH] arm64: dts: mediatek: Split PCIe node for MT2712 and MT7622
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There are two independent PCIe controllers in MT2712 and MT7622
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platform. Each of them should contain an independent MSI domain.
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In old dts architecture, MSI domain will be inherited from the root
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bridge, and all of the devices will share the same MSI domain.
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Hence that, the PCIe devices will not work properly if the irq number
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which required is more than 32.
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Split the PCIe node for MT2712 and MT7622 platform to comply with
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the hardware design and fix MSI issue.
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Signed-off-by: Chuanjia Liu <chuanjia.liu@mediatek.com>
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Acked-by: Ryder Lee <ryder.lee@mediatek.com>
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Link: https://lore.kernel.org/r/20210823032800.1660-6-chuanjia.liu@mediatek.com
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Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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---
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--- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
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@@ -915,64 +915,67 @@
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};
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};
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- pcie: pcie@11700000 {
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+ pcie1: pcie@112ff000 {
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compatible = "mediatek,mt2712-pcie";
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device_type = "pci";
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- reg = <0 0x11700000 0 0x1000>,
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- <0 0x112ff000 0 0x1000>;
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- reg-names = "port0", "port1";
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+ reg = <0 0x112ff000 0 0x1000>;
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+ reg-names = "port1";
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+ linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
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- <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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- clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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- <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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- <&pericfg CLK_PERI_PCIE0>,
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+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>,
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<&pericfg CLK_PERI_PCIE1>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1";
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- phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>;
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- phy-names = "pcie-phy0", "pcie-phy1";
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+ clock-names = "sys_ck1", "ahb_ck1";
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+ phys = <&u3port1 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy1";
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bus-range = <0x00 0xff>;
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- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>;
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+ status = "disabled";
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- pcie0: pcie@0,0 {
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- device_type = "pci";
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- status = "disabled";
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- reg = <0x0000 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <1>;
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- ranges;
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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- <0 0 0 2 &pcie_intc0 1>,
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- <0 0 0 3 &pcie_intc0 2>,
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- <0 0 0 4 &pcie_intc0 3>;
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- pcie_intc0: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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};
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+ };
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+
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+ pcie0: pcie@11700000 {
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+ compatible = "mediatek,mt2712-pcie";
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+ device_type = "pci";
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+ reg = <0 0x11700000 0 0x1000>;
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+ reg-names = "port0";
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+ linux,pci-domain = <0>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>,
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+ <&pericfg CLK_PERI_PCIE0>;
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+ clock-names = "sys_ck0", "ahb_ck0";
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+ phys = <&u3port0 PHY_TYPE_PCIE>;
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+ phy-names = "pcie-phy0";
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ status = "disabled";
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- pcie1: pcie@1,0 {
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- device_type = "pci";
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- status = "disabled";
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- reg = <0x0800 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <1>;
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- ranges;
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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- <0 0 0 2 &pcie_intc1 1>,
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- <0 0 0 3 &pcie_intc1 2>,
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- <0 0 0 4 &pcie_intc1 3>;
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- pcie_intc1: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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};
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};
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--- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
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@@ -302,18 +302,16 @@
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};
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};
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-&pcie {
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+&pcie0 {
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pinctrl-names = "default";
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- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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+};
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- pcie@0,0 {
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- status = "okay";
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- };
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-
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- pcie@1,0 {
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- status = "okay";
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- };
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+&pcie1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie1_pins>;
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+ status = "okay";
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};
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&pio {
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -232,18 +232,16 @@
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};
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};
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-&pcie {
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+&pcie0 {
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pinctrl-names = "default";
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- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
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+ pinctrl-0 = <&pcie0_pins>;
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status = "okay";
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+};
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- pcie@0,0 {
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- status = "okay";
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- };
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-
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- pcie@1,0 {
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- status = "okay";
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- };
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+&pcie1 {
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&pcie1_pins>;
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+ status = "okay";
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};
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&pio {
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -809,75 +809,83 @@
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#reset-cells = <1>;
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};
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- pcie: pcie@1a140000 {
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+ pciecfg: pciecfg@1a140000 {
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+ compatible = "mediatek,generic-pciecfg", "syscon";
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+ reg = <0 0x1a140000 0 0x1000>;
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+ };
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+
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+ pcie0: pcie@1a143000 {
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compatible = "mediatek,mt7622-pcie";
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device_type = "pci";
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- reg = <0 0x1a140000 0 0x1000>,
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- <0 0x1a143000 0 0x1000>,
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- <0 0x1a145000 0 0x1000>;
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- reg-names = "subsys", "port0", "port1";
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+ reg = <0 0x1a143000 0 0x1000>;
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+ reg-names = "port0";
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+ linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
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- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie_irq";
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clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
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- <&pciesys CLK_PCIE_P1_MAC_EN>,
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- <&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AHB_EN>,
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<&pciesys CLK_PCIE_P0_AUX_EN>,
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- <&pciesys CLK_PCIE_P1_AUX_EN>,
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<&pciesys CLK_PCIE_P0_AXI_EN>,
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- <&pciesys CLK_PCIE_P1_AXI_EN>,
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<&pciesys CLK_PCIE_P0_OBFF_EN>,
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- <&pciesys CLK_PCIE_P1_OBFF_EN>,
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- <&pciesys CLK_PCIE_P0_PIPE_EN>,
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- <&pciesys CLK_PCIE_P1_PIPE_EN>;
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- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
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- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
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- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
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+ <&pciesys CLK_PCIE_P0_PIPE_EN>;
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+ clock-names = "sys_ck0", "ahb_ck0", "aux_ck0",
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+ "axi_ck0", "obff_ck0", "pipe_ck0";
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+
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power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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bus-range = <0x00 0xff>;
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- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
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+ ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x8000000>;
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status = "disabled";
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- pcie0: pcie@0,0 {
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- reg = <0x0000 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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+ <0 0 0 2 &pcie_intc0 1>,
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+ <0 0 0 3 &pcie_intc0 2>,
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+ <0 0 0 4 &pcie_intc0 3>;
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+ pcie_intc0: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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#interrupt-cells = <1>;
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- ranges;
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- status = "disabled";
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-
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
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- <0 0 0 2 &pcie_intc0 1>,
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- <0 0 0 3 &pcie_intc0 2>,
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- <0 0 0 4 &pcie_intc0 3>;
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- pcie_intc0: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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};
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+ };
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- pcie1: pcie@1,0 {
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- reg = <0x0800 0 0 0 0>;
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- #address-cells = <3>;
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- #size-cells = <2>;
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- #interrupt-cells = <1>;
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- ranges;
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- status = "disabled";
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+ pcie1: pcie@1a145000 {
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+ compatible = "mediatek,mt7622-pcie";
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+ device_type = "pci";
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+ reg = <0 0x1a145000 0 0x1000>;
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+ reg-names = "port1";
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+ linux,pci-domain = <1>;
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+ #address-cells = <3>;
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+ #size-cells = <2>;
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+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
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+ interrupt-names = "pcie_irq";
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+ clocks = <&pciesys CLK_PCIE_P1_MAC_EN>,
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+ /* designer has connect RC1 with p0_ahb clock */
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+ <&pciesys CLK_PCIE_P0_AHB_EN>,
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+ <&pciesys CLK_PCIE_P1_AUX_EN>,
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+ <&pciesys CLK_PCIE_P1_AXI_EN>,
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+ <&pciesys CLK_PCIE_P1_OBFF_EN>,
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+ <&pciesys CLK_PCIE_P1_PIPE_EN>;
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+ clock-names = "sys_ck1", "ahb_ck1", "aux_ck1",
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+ "axi_ck1", "obff_ck1", "pipe_ck1";
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+
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+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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+ bus-range = <0x00 0xff>;
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+ ranges = <0x82000000 0 0x28000000 0x0 0x28000000 0 0x8000000>;
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+ status = "disabled";
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- interrupt-map-mask = <0 0 0 7>;
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- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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- <0 0 0 2 &pcie_intc1 1>,
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- <0 0 0 3 &pcie_intc1 2>,
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- <0 0 0 4 &pcie_intc1 3>;
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- pcie_intc1: interrupt-controller {
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- interrupt-controller;
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- #address-cells = <0>;
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- #interrupt-cells = <1>;
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- };
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+ #interrupt-cells = <1>;
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+ interrupt-map-mask = <0 0 0 7>;
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+ interrupt-map = <0 0 0 1 &pcie_intc1 0>,
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+ <0 0 0 2 &pcie_intc1 1>,
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+ <0 0 0 3 &pcie_intc1 2>,
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+ <0 0 0 4 &pcie_intc1 3>;
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+ pcie_intc1: interrupt-controller {
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+ interrupt-controller;
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+ #address-cells = <0>;
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+ #interrupt-cells = <1>;
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};
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};
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