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d6a9a92e32
Seemingly unneeded based on new upstream code so manually deleted: layerscape: 820-usb-0007-usb-dwc3-gadget-increase-timeout-value-for-send-ep-c.patch Manually merged: generic-hack: 251-sound_kconfig.patch All other modifications made by update_kernel.sh Build system: x86_64 Build-tested: ipq806x/R7800, ath79/generic, bcm27xx/bcm2711 Run-tested: ipq806x/R7800, lantiq/Easybox 904 xDSL No dmesg regressions, everything functional Signed-off-by: John Audia <graysky@archlinux.us> [add lantiq test report, minor commit message clarification] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
203 lines
6.4 KiB
Diff
203 lines
6.4 KiB
Diff
From 73b0aa73b401810424afa90bf58663a56ad9d51a Mon Sep 17 00:00:00 2001
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From: Ioana Radulescu <ruxandra.radulescu@nxp.com>
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Date: Fri, 5 May 2017 19:07:50 +0300
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Subject: [PATCH] dpaa2-eth: Add Rx error queue
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Until now all error frames on the ingress path were discarded
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in hardware. For debug purposes, add an option to have these
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frames delivered to the cpu, on a dedicated queue.
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TODO: Remove Kconfig option, find another way to enable
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Rx error queue support
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Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
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---
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drivers/net/ethernet/freescale/dpaa2/Kconfig | 10 +++
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drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c | 97 ++++++++++++++++++++++++
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drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h | 5 +-
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3 files changed, 111 insertions(+), 1 deletion(-)
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--- a/drivers/net/ethernet/freescale/dpaa2/Kconfig
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+++ b/drivers/net/ethernet/freescale/dpaa2/Kconfig
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@@ -15,6 +15,16 @@ config FSL_DPAA2_ETH_DCB
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depends on DCB
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help
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Enable Priority-Based Flow Control (PFC) support in the driver
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+
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+config FSL_DPAA2_ETH_USE_ERR_QUEUE
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+ bool "Enable Rx error queue"
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+ default n
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+ help
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+ Allow Rx error frames to be enqueued on an error queue
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+ and processed by the driver (by default they are dropped
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+ in hardware).
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+ This may impact performance, recommended for debugging
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+ purposes only.
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endif
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config FSL_DPAA2_PTP_CLOCK
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--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
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+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.c
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@@ -449,6 +449,53 @@ err_frame_format:
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percpu_stats->rx_dropped++;
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}
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+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
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+/* Processing of Rx frames received on the error FQ
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+ * We check and print the error bits and then free the frame
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+ */
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+static void dpaa2_eth_rx_err(struct dpaa2_eth_priv *priv,
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+ struct dpaa2_eth_channel *ch,
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+ const struct dpaa2_fd *fd,
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+ struct dpaa2_eth_fq *fq __always_unused)
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+{
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+ struct device *dev = priv->net_dev->dev.parent;
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+ dma_addr_t addr = dpaa2_fd_get_addr(fd);
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+ void *vaddr;
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+ struct rtnl_link_stats64 *percpu_stats;
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+ struct dpaa2_fas *fas;
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+ u32 status = 0;
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+ u32 fd_errors;
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+ bool has_fas_errors = false;
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+
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+ vaddr = dpaa2_iova_to_virt(priv->iommu_domain, addr);
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+ dma_unmap_single(dev, addr, DPAA2_ETH_RX_BUF_SIZE, DMA_BIDIRECTIONAL);
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+
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+ /* check frame errors in the FD field */
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+ fd_errors = dpaa2_fd_get_ctrl(fd) & DPAA2_FD_RX_ERR_MASK;
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+ if (likely(fd_errors)) {
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+ has_fas_errors = (fd_errors & FD_CTRL_FAERR) &&
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+ !!(dpaa2_fd_get_frc(fd) & DPAA2_FD_FRC_FASV);
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+ if (net_ratelimit())
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+ netdev_dbg(priv->net_dev, "RX frame FD err: %08x\n",
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+ fd_errors);
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+ }
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+
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+ /* check frame errors in the FAS field */
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+ if (has_fas_errors) {
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+ fas = dpaa2_get_fas(vaddr, false);
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+ status = le32_to_cpu(fas->status);
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+ if (net_ratelimit())
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+ netdev_dbg(priv->net_dev, "Rx frame FAS err: 0x%08x\n",
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+ status & DPAA2_FAS_RX_ERR_MASK);
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+ }
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+ free_rx_fd(priv, fd, vaddr);
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+
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+ percpu_stats = this_cpu_ptr(priv->percpu_stats);
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+ percpu_stats->rx_errors++;
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+ ch->buf_count--;
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+}
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+#endif
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+
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/* Consume all frames pull-dequeued into the store. This is the simplest way to
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* make sure we don't accidentally issue another volatile dequeue which would
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* overwrite (leak) frames already in the store.
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@@ -2351,6 +2398,7 @@ static void set_fq_affinity(struct dpaa2
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fq = &priv->fq[i];
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switch (fq->type) {
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case DPAA2_RX_FQ:
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+ case DPAA2_RX_ERR_FQ:
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fq->target_cpu = rx_cpu;
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rx_cpu = cpumask_next(rx_cpu, &priv->dpio_cpumask);
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if (rx_cpu >= nr_cpu_ids)
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@@ -2394,6 +2442,12 @@ static void setup_fqs(struct dpaa2_eth_p
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}
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}
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+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
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+ /* We have exactly one Rx error queue per DPNI */
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+ priv->fq[priv->num_fqs].type = DPAA2_RX_ERR_FQ;
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+ priv->fq[priv->num_fqs++].consume = dpaa2_eth_rx_err;
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+#endif
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+
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/* For each FQ, decide on which core to process incoming frames */
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set_fq_affinity(priv);
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}
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@@ -2946,6 +3000,40 @@ static int setup_tx_flow(struct dpaa2_et
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return 0;
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}
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+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
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+static int setup_rx_err_flow(struct dpaa2_eth_priv *priv,
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+ struct dpaa2_eth_fq *fq)
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+{
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+ struct device *dev = priv->net_dev->dev.parent;
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+ struct dpni_queue q = { { 0 } };
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+ struct dpni_queue_id qid;
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+ u8 q_opt = DPNI_QUEUE_OPT_USER_CTX | DPNI_QUEUE_OPT_DEST;
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+ int err;
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+
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+ err = dpni_get_queue(priv->mc_io, 0, priv->mc_token,
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+ DPNI_QUEUE_RX_ERR, 0, 0, &q, &qid);
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+ if (err) {
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+ dev_err(dev, "dpni_get_queue() failed (%d)\n", err);
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+ return err;
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+ }
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+
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+ fq->fqid = qid.fqid;
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+
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+ q.destination.id = fq->channel->dpcon_id;
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+ q.destination.type = DPNI_DEST_DPCON;
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+ q.destination.priority = 1;
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+ q.user_context = (u64)fq;
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+ err = dpni_set_queue(priv->mc_io, 0, priv->mc_token,
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+ DPNI_QUEUE_RX_ERR, 0, 0, q_opt, &q);
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+ if (err) {
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+ dev_err(dev, "dpni_set_queue() failed (%d)\n", err);
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+ return err;
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+ }
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+
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+ return 0;
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+}
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+#endif
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+
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/* Supported header fields for Rx hash distribution key */
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static const struct dpaa2_eth_dist_fields dist_fields[] = {
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{
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@@ -3315,7 +3403,11 @@ static int bind_dpni(struct dpaa2_eth_pr
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/* Configure handling of error frames */
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err_cfg.errors = DPAA2_FAS_RX_ERR_MASK;
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err_cfg.set_frame_annotation = 1;
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+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
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+ err_cfg.error_action = DPNI_ERROR_ACTION_SEND_TO_ERROR_QUEUE;
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+#else
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err_cfg.error_action = DPNI_ERROR_ACTION_DISCARD;
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+#endif
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err = dpni_set_errors_behavior(priv->mc_io, 0, priv->mc_token,
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&err_cfg);
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if (err) {
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@@ -3332,6 +3424,11 @@ static int bind_dpni(struct dpaa2_eth_pr
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case DPAA2_TX_CONF_FQ:
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err = setup_tx_flow(priv, &priv->fq[i]);
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break;
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+#ifdef CONFIG_FSL_DPAA2_ETH_USE_ERR_QUEUE
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+ case DPAA2_RX_ERR_FQ:
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+ err = setup_rx_err_flow(priv, &priv->fq[i]);
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+ break;
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+#endif
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default:
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dev_err(dev, "Invalid FQ type %d\n", priv->fq[i].type);
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return -EINVAL;
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--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h
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+++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-eth.h
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@@ -318,8 +318,10 @@ struct dpaa2_eth_ch_stats {
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#define DPAA2_ETH_MAX_RX_QUEUES \
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(DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
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#define DPAA2_ETH_MAX_TX_QUEUES 16
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+#define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
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#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
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- DPAA2_ETH_MAX_TX_QUEUES)
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+ DPAA2_ETH_MAX_TX_QUEUES + \
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+ DPAA2_ETH_MAX_RX_ERR_QUEUES)
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#define DPAA2_ETH_MAX_NETDEV_QUEUES \
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(DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
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@@ -328,6 +330,7 @@ struct dpaa2_eth_ch_stats {
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enum dpaa2_eth_fq_type {
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DPAA2_RX_FQ = 0,
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DPAA2_TX_CONF_FQ,
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+ DPAA2_RX_ERR_FQ
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};
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struct dpaa2_eth_priv;
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