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029093a302
This target has full device tree support, thus reducing the number of patches needed for bcm63xx, in which there's a patch for every board. The intention is to start with a minimal amount of downstream patches and start upstreaming all of them. Current status: - Enabling EHCI/OHCI on BCM6358 causes a kernel panic. - BCM63268 lacks Timer Clocks/Reset support. - No PCI/PCIe drivers. - No ethernet drivers. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com> Acked-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
72 lines
2.3 KiB
C
72 lines
2.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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#ifndef __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H
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#define __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H
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#define BCM6368_IRQ_TIMER 0
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#define BCM6368_IRQ_SPI 1
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#define BCM6368_IRQ_UART0 2
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#define BCM6368_IRQ_UART1 3
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#define BCM6368_IRQ_XDSL 4
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#define BCM6368_IRQ_OHCI 5
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#define BCM6368_IRQ_IPSEC 6
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#define BCM6368_IRQ_EHCI 7
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#define BCM6368_IRQ_USBS 8
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#define BCM6368_IRQ_RING_OSC 9
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#define BCM6368_IRQ_NAND 10
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#define BCM6368_IRQ_ATM 11
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#define BCM6368_IRQ_PCM 12
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#define BCM6368_IRQ_MPI 13
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#define BCM6368_IRQ_DG 14
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#define BCM6368_IRQ_EPHY 15
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#define BCM6368_IRQ_EPHY_EN0 16
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#define BCM6368_IRQ_EPHY_EN1 17
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#define BCM6368_IRQ_EPHY_EN2 18
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#define BCM6368_IRQ_EPHY_EN3 19
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#define BCM6368_IRQ_EXT0 20
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#define BCM6368_IRQ_EXT1 21
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#define BCM6368_IRQ_EXT2 22
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#define BCM6368_IRQ_EXT3 23
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#define BCM6368_IRQ_EXT4 24
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#define BCM6368_IRQ_EXT5 25
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#define BCM6368_IRQ_USB_CTL_RX_DMA 26
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#define BCM6368_IRQ_USB_CTL_TX_DMA 27
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#define BCM6368_IRQ_USB_BULK_RX_DMA 28
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#define BCM6368_IRQ_USB_BULK_TX_DMA 29
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#define BCM6368_IRQ_USB_ISO_RX_DMA 30
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#define BCM6368_IRQ_USB_ISO_TX_DMA 31
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#define BCM6368_IRQ_ENETSW_RX_DMA0 32
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#define BCM6368_IRQ_ENETSW_RX_DMA1 33
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#define BCM6368_IRQ_ENETSW_RX_DMA2 34
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#define BCM6368_IRQ_ENETSW_RX_DMA3 35
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#define BCM6368_IRQ_ENETSW_TX_DMA0 36
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#define BCM6368_IRQ_ENETSW_TX_DMA1 37
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#define BCM6368_IRQ_ENETSW_TX_DMA2 38
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#define BCM6368_IRQ_ENETSW_TX_DMA3 39
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#define BCM6368_IRQ_ATM_DMA0 40
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#define BCM6368_IRQ_ATM_DMA1 41
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#define BCM6368_IRQ_ATM_DMA2 42
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#define BCM6368_IRQ_ATM_DMA3 43
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#define BCM6368_IRQ_ATM_DMA4 44
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#define BCM6368_IRQ_ATM_DMA5 45
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#define BCM6368_IRQ_ATM_DMA6 46
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#define BCM6368_IRQ_ATM_DMA7 47
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#define BCM6368_IRQ_ATM_DMA8 48
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#define BCM6368_IRQ_ATM_DMA9 49
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#define BCM6368_IRQ_ATM_DMA10 50
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#define BCM6368_IRQ_ATM_DMA11 51
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#define BCM6368_IRQ_ATM_DMA12 52
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#define BCM6368_IRQ_ATM_DMA13 53
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#define BCM6368_IRQ_ATM_DMA14 54
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#define BCM6368_IRQ_ATM_DMA15 55
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#define BCM6368_IRQ_ATM_DMA16 56
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#define BCM6368_IRQ_ATM_DMA17 57
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#define BCM6368_IRQ_ATM_DMA18 58
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#define BCM6368_IRQ_ATM_DMA19 59
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#define BCM6368_IRQ_IPSEC_DMA0 60
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#define BCM6368_IRQ_IPSEC_DMA1 61
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#define BCM6368_IRQ_PCM_DMA0 62
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#define BCM6368_IRQ_PCM_DMA1 63
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#endif /* __DT_BINDINGS_INTERRUPT_CONTROLLER_BCM6368_H */
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