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08d8a3646b
These patches have been accepted for linux v5.13. External interrupts not supported for now. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
577 lines
15 KiB
Diff
577 lines
15 KiB
Diff
From 50554accf7a79980cd04481e8903073bdb706daf Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
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Date: Wed, 24 Mar 2021 09:19:17 +0100
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Subject: [PATCH 16/22] pinctrl: add a pincontrol driver for BCM6368
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Add a pincontrol driver for BCM6368. BCM6368 allows muxing the first 32
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GPIOs onto alternative functions. Not all are documented.
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Co-developed-by: Jonas Gorski <jonas.gorski@gmail.com>
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Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
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Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
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Link: https://lore.kernel.org/r/20210324081923.20379-17-noltari@gmail.com
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Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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---
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drivers/pinctrl/bcm/Kconfig | 8 +
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drivers/pinctrl/bcm/Makefile | 1 +
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drivers/pinctrl/bcm/pinctrl-bcm6368.c | 523 ++++++++++++++++++++++++++
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3 files changed, 532 insertions(+)
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create mode 100644 drivers/pinctrl/bcm/pinctrl-bcm6368.c
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--- a/drivers/pinctrl/bcm/Kconfig
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+++ b/drivers/pinctrl/bcm/Kconfig
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@@ -60,6 +60,14 @@ config PINCTRL_BCM6362
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help
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Say Y here to enable the Broadcom BCM6362 GPIO driver.
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+config PINCTRL_BCM6368
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+ bool "Broadcom BCM6368 GPIO driver"
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+ depends on (BMIPS_GENERIC || COMPILE_TEST)
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+ select PINCTRL_BCM63XX
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+ default BMIPS_GENERIC
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+ help
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+ Say Y here to enable the Broadcom BCM6368 GPIO driver.
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+
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config PINCTRL_IPROC_GPIO
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bool "Broadcom iProc GPIO (with PINCONF) driver"
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depends on OF_GPIO && (ARCH_BCM_IPROC || COMPILE_TEST)
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--- a/drivers/pinctrl/bcm/Makefile
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+++ b/drivers/pinctrl/bcm/Makefile
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@@ -7,6 +7,7 @@ obj-$(CONFIG_PINCTRL_BCM63XX) += pinctr
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obj-$(CONFIG_PINCTRL_BCM6328) += pinctrl-bcm6328.o
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obj-$(CONFIG_PINCTRL_BCM6358) += pinctrl-bcm6358.o
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obj-$(CONFIG_PINCTRL_BCM6362) += pinctrl-bcm6362.o
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+obj-$(CONFIG_PINCTRL_BCM6368) += pinctrl-bcm6368.o
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obj-$(CONFIG_PINCTRL_IPROC_GPIO) += pinctrl-iproc-gpio.o
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obj-$(CONFIG_PINCTRL_CYGNUS_MUX) += pinctrl-cygnus-mux.o
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obj-$(CONFIG_PINCTRL_NS) += pinctrl-ns.o
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--- /dev/null
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+++ b/drivers/pinctrl/bcm/pinctrl-bcm6368.c
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@@ -0,0 +1,523 @@
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+// SPDX-License-Identifier: GPL-2.0+
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+/*
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+ * Driver for BCM6368 GPIO unit (pinctrl + GPIO)
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+ *
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+ * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
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+ * Copyright (C) 2016 Jonas Gorski <jonas.gorski@gmail.com>
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+ */
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+
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+#include <linux/bits.h>
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+#include <linux/gpio/driver.h>
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+#include <linux/kernel.h>
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+#include <linux/of.h>
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+#include <linux/pinctrl/pinmux.h>
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+#include <linux/platform_device.h>
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+#include <linux/regmap.h>
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+
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+#include "../pinctrl-utils.h"
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+
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+#include "pinctrl-bcm63xx.h"
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+
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+#define BCM6368_NUM_GPIOS 38
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+
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+#define BCM6368_MODE_REG 0x18
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+#define BCM6368_BASEMODE_REG 0x38
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+#define BCM6368_BASEMODE_MASK 0x7
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+#define BCM6368_BASEMODE_GPIO 0x0
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+#define BCM6368_BASEMODE_UART1 0x1
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+
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+struct bcm6368_pingroup {
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+ const char *name;
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+ const unsigned * const pins;
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+ const unsigned num_pins;
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+};
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+
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+struct bcm6368_function {
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+ const char *name;
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+ const char * const *groups;
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+ const unsigned num_groups;
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+
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+ unsigned dir_out:16;
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+ unsigned basemode:3;
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+};
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+
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+struct bcm6368_priv {
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+ struct regmap_field *overlays;
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+};
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+
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+#define BCM6368_BASEMODE_PIN(a, b) \
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+ { \
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+ .number = a, \
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+ .name = b, \
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+ .drv_data = (void *)true \
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+ }
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+
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+static const struct pinctrl_pin_desc bcm6368_pins[] = {
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+ PINCTRL_PIN(0, "gpio0"),
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+ PINCTRL_PIN(1, "gpio1"),
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+ PINCTRL_PIN(2, "gpio2"),
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+ PINCTRL_PIN(3, "gpio3"),
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+ PINCTRL_PIN(4, "gpio4"),
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+ PINCTRL_PIN(5, "gpio5"),
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+ PINCTRL_PIN(6, "gpio6"),
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+ PINCTRL_PIN(7, "gpio7"),
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+ PINCTRL_PIN(8, "gpio8"),
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+ PINCTRL_PIN(9, "gpio9"),
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+ PINCTRL_PIN(10, "gpio10"),
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+ PINCTRL_PIN(11, "gpio11"),
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+ PINCTRL_PIN(12, "gpio12"),
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+ PINCTRL_PIN(13, "gpio13"),
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+ PINCTRL_PIN(14, "gpio14"),
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+ PINCTRL_PIN(15, "gpio15"),
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+ PINCTRL_PIN(16, "gpio16"),
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+ PINCTRL_PIN(17, "gpio17"),
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+ PINCTRL_PIN(18, "gpio18"),
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+ PINCTRL_PIN(19, "gpio19"),
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+ PINCTRL_PIN(20, "gpio20"),
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+ PINCTRL_PIN(21, "gpio21"),
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+ PINCTRL_PIN(22, "gpio22"),
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+ PINCTRL_PIN(23, "gpio23"),
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+ PINCTRL_PIN(24, "gpio24"),
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+ PINCTRL_PIN(25, "gpio25"),
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+ PINCTRL_PIN(26, "gpio26"),
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+ PINCTRL_PIN(27, "gpio27"),
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+ PINCTRL_PIN(28, "gpio28"),
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+ PINCTRL_PIN(29, "gpio29"),
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+ BCM6368_BASEMODE_PIN(30, "gpio30"),
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+ BCM6368_BASEMODE_PIN(31, "gpio31"),
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+ BCM6368_BASEMODE_PIN(32, "gpio32"),
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+ BCM6368_BASEMODE_PIN(33, "gpio33"),
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+ PINCTRL_PIN(34, "gpio34"),
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+ PINCTRL_PIN(35, "gpio35"),
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+ PINCTRL_PIN(36, "gpio36"),
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+ PINCTRL_PIN(37, "gpio37"),
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+};
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+
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+static unsigned gpio0_pins[] = { 0 };
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+static unsigned gpio1_pins[] = { 1 };
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+static unsigned gpio2_pins[] = { 2 };
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+static unsigned gpio3_pins[] = { 3 };
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+static unsigned gpio4_pins[] = { 4 };
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+static unsigned gpio5_pins[] = { 5 };
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+static unsigned gpio6_pins[] = { 6 };
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+static unsigned gpio7_pins[] = { 7 };
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+static unsigned gpio8_pins[] = { 8 };
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+static unsigned gpio9_pins[] = { 9 };
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+static unsigned gpio10_pins[] = { 10 };
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+static unsigned gpio11_pins[] = { 11 };
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+static unsigned gpio12_pins[] = { 12 };
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+static unsigned gpio13_pins[] = { 13 };
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+static unsigned gpio14_pins[] = { 14 };
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+static unsigned gpio15_pins[] = { 15 };
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+static unsigned gpio16_pins[] = { 16 };
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+static unsigned gpio17_pins[] = { 17 };
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+static unsigned gpio18_pins[] = { 18 };
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+static unsigned gpio19_pins[] = { 19 };
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+static unsigned gpio20_pins[] = { 20 };
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+static unsigned gpio21_pins[] = { 21 };
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+static unsigned gpio22_pins[] = { 22 };
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+static unsigned gpio23_pins[] = { 23 };
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+static unsigned gpio24_pins[] = { 24 };
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+static unsigned gpio25_pins[] = { 25 };
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+static unsigned gpio26_pins[] = { 26 };
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+static unsigned gpio27_pins[] = { 27 };
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+static unsigned gpio28_pins[] = { 28 };
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+static unsigned gpio29_pins[] = { 29 };
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+static unsigned gpio30_pins[] = { 30 };
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+static unsigned gpio31_pins[] = { 31 };
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+static unsigned uart1_grp_pins[] = { 30, 31, 32, 33 };
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+
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+#define BCM6368_GROUP(n) \
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+ { \
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+ .name = #n, \
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+ .pins = n##_pins, \
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+ .num_pins = ARRAY_SIZE(n##_pins), \
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+ }
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+
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+static struct bcm6368_pingroup bcm6368_groups[] = {
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+ BCM6368_GROUP(gpio0),
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+ BCM6368_GROUP(gpio1),
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+ BCM6368_GROUP(gpio2),
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+ BCM6368_GROUP(gpio3),
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+ BCM6368_GROUP(gpio4),
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+ BCM6368_GROUP(gpio5),
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+ BCM6368_GROUP(gpio6),
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+ BCM6368_GROUP(gpio7),
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+ BCM6368_GROUP(gpio8),
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+ BCM6368_GROUP(gpio9),
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+ BCM6368_GROUP(gpio10),
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+ BCM6368_GROUP(gpio11),
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+ BCM6368_GROUP(gpio12),
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+ BCM6368_GROUP(gpio13),
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+ BCM6368_GROUP(gpio14),
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+ BCM6368_GROUP(gpio15),
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+ BCM6368_GROUP(gpio16),
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+ BCM6368_GROUP(gpio17),
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+ BCM6368_GROUP(gpio18),
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+ BCM6368_GROUP(gpio19),
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+ BCM6368_GROUP(gpio20),
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+ BCM6368_GROUP(gpio21),
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+ BCM6368_GROUP(gpio22),
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+ BCM6368_GROUP(gpio23),
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+ BCM6368_GROUP(gpio24),
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+ BCM6368_GROUP(gpio25),
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+ BCM6368_GROUP(gpio26),
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+ BCM6368_GROUP(gpio27),
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+ BCM6368_GROUP(gpio28),
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+ BCM6368_GROUP(gpio29),
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+ BCM6368_GROUP(gpio30),
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+ BCM6368_GROUP(gpio31),
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+ BCM6368_GROUP(uart1_grp),
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+};
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+
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+static const char * const analog_afe_0_groups[] = {
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+ "gpio0",
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+};
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+
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+static const char * const analog_afe_1_groups[] = {
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+ "gpio1",
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+};
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+
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+static const char * const sys_irq_groups[] = {
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+ "gpio2",
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+};
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+
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+static const char * const serial_led_data_groups[] = {
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+ "gpio3",
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+};
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+
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+static const char * const serial_led_clk_groups[] = {
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+ "gpio4",
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+};
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+
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+static const char * const inet_led_groups[] = {
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+ "gpio5",
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+};
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+
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+static const char * const ephy0_led_groups[] = {
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+ "gpio6",
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+};
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+
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+static const char * const ephy1_led_groups[] = {
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+ "gpio7",
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+};
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+
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+static const char * const ephy2_led_groups[] = {
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+ "gpio8",
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+};
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+
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+static const char * const ephy3_led_groups[] = {
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+ "gpio9",
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+};
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+
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+static const char * const robosw_led_data_groups[] = {
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+ "gpio10",
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+};
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+
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+static const char * const robosw_led_clk_groups[] = {
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+ "gpio11",
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+};
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+
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+static const char * const robosw_led0_groups[] = {
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+ "gpio12",
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+};
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+
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+static const char * const robosw_led1_groups[] = {
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+ "gpio13",
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+};
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+
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+static const char * const usb_device_led_groups[] = {
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+ "gpio14",
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+};
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+
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+static const char * const pci_req1_groups[] = {
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+ "gpio16",
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+};
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+
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+static const char * const pci_gnt1_groups[] = {
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+ "gpio17",
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+};
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+
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+static const char * const pci_intb_groups[] = {
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+ "gpio18",
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+};
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+
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+static const char * const pci_req0_groups[] = {
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+ "gpio19",
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+};
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+
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+static const char * const pci_gnt0_groups[] = {
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+ "gpio20",
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+};
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+
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+static const char * const pcmcia_cd1_groups[] = {
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+ "gpio22",
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+};
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+
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+static const char * const pcmcia_cd2_groups[] = {
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+ "gpio23",
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+};
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+
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+static const char * const pcmcia_vs1_groups[] = {
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+ "gpio24",
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+};
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+
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+static const char * const pcmcia_vs2_groups[] = {
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+ "gpio25",
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+};
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+
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+static const char * const ebi_cs2_groups[] = {
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+ "gpio26",
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+};
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+
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+static const char * const ebi_cs3_groups[] = {
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+ "gpio27",
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+};
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+
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+static const char * const spi_cs2_groups[] = {
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+ "gpio28",
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+};
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+
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+static const char * const spi_cs3_groups[] = {
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+ "gpio29",
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+};
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+
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+static const char * const spi_cs4_groups[] = {
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+ "gpio30",
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+};
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+
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+static const char * const spi_cs5_groups[] = {
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+ "gpio31",
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+};
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+
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+static const char * const uart1_groups[] = {
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+ "uart1_grp",
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+};
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+
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+#define BCM6368_FUN(n, out) \
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+ { \
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+ .name = #n, \
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+ .groups = n##_groups, \
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+ .num_groups = ARRAY_SIZE(n##_groups), \
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+ .dir_out = out, \
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+ }
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+
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+#define BCM6368_BASEMODE_FUN(n, val, out) \
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+ { \
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+ .name = #n, \
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+ .groups = n##_groups, \
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+ .num_groups = ARRAY_SIZE(n##_groups), \
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+ .basemode = BCM6368_BASEMODE_##val, \
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+ .dir_out = out, \
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+ }
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+
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+static const struct bcm6368_function bcm6368_funcs[] = {
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+ BCM6368_FUN(analog_afe_0, 1),
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+ BCM6368_FUN(analog_afe_1, 1),
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+ BCM6368_FUN(sys_irq, 1),
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+ BCM6368_FUN(serial_led_data, 1),
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+ BCM6368_FUN(serial_led_clk, 1),
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+ BCM6368_FUN(inet_led, 1),
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+ BCM6368_FUN(ephy0_led, 1),
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+ BCM6368_FUN(ephy1_led, 1),
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+ BCM6368_FUN(ephy2_led, 1),
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+ BCM6368_FUN(ephy3_led, 1),
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+ BCM6368_FUN(robosw_led_data, 1),
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+ BCM6368_FUN(robosw_led_clk, 1),
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+ BCM6368_FUN(robosw_led0, 1),
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+ BCM6368_FUN(robosw_led1, 1),
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+ BCM6368_FUN(usb_device_led, 1),
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+ BCM6368_FUN(pci_req1, 0),
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+ BCM6368_FUN(pci_gnt1, 0),
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+ BCM6368_FUN(pci_intb, 0),
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+ BCM6368_FUN(pci_req0, 0),
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+ BCM6368_FUN(pci_gnt0, 0),
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+ BCM6368_FUN(pcmcia_cd1, 0),
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+ BCM6368_FUN(pcmcia_cd2, 0),
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+ BCM6368_FUN(pcmcia_vs1, 0),
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+ BCM6368_FUN(pcmcia_vs2, 0),
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+ BCM6368_FUN(ebi_cs2, 1),
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+ BCM6368_FUN(ebi_cs3, 1),
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+ BCM6368_FUN(spi_cs2, 1),
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+ BCM6368_FUN(spi_cs3, 1),
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+ BCM6368_FUN(spi_cs4, 1),
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+ BCM6368_FUN(spi_cs5, 1),
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+ BCM6368_BASEMODE_FUN(uart1, UART1, 0x6),
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+};
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+
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+static int bcm6368_pinctrl_get_group_count(struct pinctrl_dev *pctldev)
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+{
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+ return ARRAY_SIZE(bcm6368_groups);
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+}
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+
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+static const char *bcm6368_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
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+ unsigned group)
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+{
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+ return bcm6368_groups[group].name;
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+}
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+
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+static int bcm6368_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
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+ unsigned group, const unsigned **pins,
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+ unsigned *num_pins)
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+{
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+ *pins = bcm6368_groups[group].pins;
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+ *num_pins = bcm6368_groups[group].num_pins;
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+
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+ return 0;
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+}
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+
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+static int bcm6368_pinctrl_get_func_count(struct pinctrl_dev *pctldev)
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+{
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+ return ARRAY_SIZE(bcm6368_funcs);
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+}
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+
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+static const char *bcm6368_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
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+ unsigned selector)
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+{
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+ return bcm6368_funcs[selector].name;
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+}
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+
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+static int bcm6368_pinctrl_get_groups(struct pinctrl_dev *pctldev,
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+ unsigned selector,
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+ const char * const **groups,
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+ unsigned * const num_groups)
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+{
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+ *groups = bcm6368_funcs[selector].groups;
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+ *num_groups = bcm6368_funcs[selector].num_groups;
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+
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+ return 0;
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+}
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+
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+static int bcm6368_pinctrl_set_mux(struct pinctrl_dev *pctldev,
|
|
+ unsigned selector, unsigned group)
|
|
+{
|
|
+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
|
|
+ struct bcm6368_priv *priv = pc->driver_data;
|
|
+ const struct bcm6368_pingroup *pg = &bcm6368_groups[group];
|
|
+ const struct bcm6368_function *fun = &bcm6368_funcs[selector];
|
|
+ int i, pin;
|
|
+
|
|
+ if (fun->basemode) {
|
|
+ unsigned int mask = 0;
|
|
+
|
|
+ for (i = 0; i < pg->num_pins; i++) {
|
|
+ pin = pg->pins[i];
|
|
+ if (pin < BCM63XX_BANK_GPIOS)
|
|
+ mask |= BIT(pin);
|
|
+ }
|
|
+
|
|
+ regmap_update_bits(pc->regs, BCM6368_MODE_REG, mask, 0);
|
|
+ regmap_field_write(priv->overlays, fun->basemode);
|
|
+ } else {
|
|
+ pin = pg->pins[0];
|
|
+
|
|
+ if (bcm6368_pins[pin].drv_data)
|
|
+ regmap_field_write(priv->overlays,
|
|
+ BCM6368_BASEMODE_GPIO);
|
|
+
|
|
+ regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(pin),
|
|
+ BIT(pin));
|
|
+ }
|
|
+
|
|
+ for (pin = 0; pin < pg->num_pins; pin++) {
|
|
+ struct pinctrl_gpio_range *range;
|
|
+ int hw_gpio = bcm6368_pins[pin].number;
|
|
+
|
|
+ range = pinctrl_find_gpio_range_from_pin(pctldev, hw_gpio);
|
|
+ if (range) {
|
|
+ struct gpio_chip *gc = range->gc;
|
|
+
|
|
+ if (fun->dir_out & BIT(pin))
|
|
+ gc->direction_output(gc, hw_gpio, 0);
|
|
+ else
|
|
+ gc->direction_input(gc, hw_gpio);
|
|
+ }
|
|
+ }
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static int bcm6368_gpio_request_enable(struct pinctrl_dev *pctldev,
|
|
+ struct pinctrl_gpio_range *range,
|
|
+ unsigned offset)
|
|
+{
|
|
+ struct bcm63xx_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
|
|
+ struct bcm6368_priv *priv = pc->driver_data;
|
|
+
|
|
+ if (offset >= BCM63XX_BANK_GPIOS && !bcm6368_pins[offset].drv_data)
|
|
+ return 0;
|
|
+
|
|
+ /* disable all functions using this pin */
|
|
+ if (offset < BCM63XX_BANK_GPIOS)
|
|
+ regmap_update_bits(pc->regs, BCM6368_MODE_REG, BIT(offset), 0);
|
|
+
|
|
+ if (bcm6368_pins[offset].drv_data)
|
|
+ regmap_field_write(priv->overlays, BCM6368_BASEMODE_GPIO);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static struct pinctrl_ops bcm6368_pctl_ops = {
|
|
+ .dt_free_map = pinctrl_utils_free_map,
|
|
+ .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
|
|
+ .get_group_name = bcm6368_pinctrl_get_group_name,
|
|
+ .get_group_pins = bcm6368_pinctrl_get_group_pins,
|
|
+ .get_groups_count = bcm6368_pinctrl_get_group_count,
|
|
+};
|
|
+
|
|
+static struct pinmux_ops bcm6368_pmx_ops = {
|
|
+ .get_function_groups = bcm6368_pinctrl_get_groups,
|
|
+ .get_function_name = bcm6368_pinctrl_get_func_name,
|
|
+ .get_functions_count = bcm6368_pinctrl_get_func_count,
|
|
+ .gpio_request_enable = bcm6368_gpio_request_enable,
|
|
+ .set_mux = bcm6368_pinctrl_set_mux,
|
|
+ .strict = true,
|
|
+};
|
|
+
|
|
+static const struct bcm63xx_pinctrl_soc bcm6368_soc = {
|
|
+ .ngpios = BCM6368_NUM_GPIOS,
|
|
+ .npins = ARRAY_SIZE(bcm6368_pins),
|
|
+ .pctl_ops = &bcm6368_pctl_ops,
|
|
+ .pins = bcm6368_pins,
|
|
+ .pmx_ops = &bcm6368_pmx_ops,
|
|
+};
|
|
+
|
|
+static int bcm6368_pinctrl_probe(struct platform_device *pdev)
|
|
+{
|
|
+ struct reg_field overlays = REG_FIELD(BCM6368_BASEMODE_REG, 0, 15);
|
|
+ struct device *dev = &pdev->dev;
|
|
+ struct bcm63xx_pinctrl *pc;
|
|
+ struct bcm6368_priv *priv;
|
|
+ int err;
|
|
+
|
|
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
|
+ if (!priv)
|
|
+ return -ENOMEM;
|
|
+
|
|
+ err = bcm63xx_pinctrl_probe(pdev, &bcm6368_soc, (void *) priv);
|
|
+ if (err)
|
|
+ return err;
|
|
+
|
|
+ pc = platform_get_drvdata(pdev);
|
|
+
|
|
+ priv->overlays = devm_regmap_field_alloc(dev, pc->regs, overlays);
|
|
+ if (IS_ERR(priv->overlays))
|
|
+ return PTR_ERR(priv->overlays);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+
|
|
+static const struct of_device_id bcm6368_pinctrl_match[] = {
|
|
+ { .compatible = "brcm,bcm6368-pinctrl", },
|
|
+ { /* sentinel */ }
|
|
+};
|
|
+
|
|
+static struct platform_driver bcm6368_pinctrl_driver = {
|
|
+ .probe = bcm6368_pinctrl_probe,
|
|
+ .driver = {
|
|
+ .name = "bcm6368-pinctrl",
|
|
+ .of_match_table = bcm6368_pinctrl_match,
|
|
+ },
|
|
+};
|
|
+
|
|
+builtin_platform_driver(bcm6368_pinctrl_driver);
|