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f32085fc0b
Airoha is a new ARM platform based on Cortex-A53 which has recently been merged into linux-next. Due to BootROM limitations on this platform, the Cortex-A53 can't run in Aarch64 mode and code must be compiled for 32-Bit ARM. This support is based mostly on those linux-next commits backported for kernel 5.15. Patches: 1 - platform support = linux-next 2 - clock driver = linux-next 3 - gpio driver = linux-next 4 - linux,usable-memory-range dts support = linux-next 5 - mtd spinand driver 6 - spi driver 7 - pci driver (kconfig only, uses mediatek PCI) = linux-next Still missing: - Ethernet driver - Sysupgrade support A.t.m there exists one subtarget EN7523 with only one evaluation board. The initramfs can be run with the following commands from u-boot: - u-boot> setenv bootfile \ openwrt-airoha-airoha_en7523-evb-initramfs-kernel.bin u-boot> tftpboot u-boot> bootm 0x81800000 - Signed-off-by: Daniel Danzberger <daniel@dd-wrt.com>
138 lines
3.3 KiB
C
138 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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#include <linux/types.h>
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#include <linux/io.h>
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#include <linux/bits.h>
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#include <linux/gpio/driver.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#define AIROHA_GPIO_MAX 32
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/**
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* airoha_gpio_ctrl - Airoha GPIO driver data
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* @gc: Associated gpio_chip instance.
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* @data: The data register.
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* @dir0: The direction register for the lower 16 pins.
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* @dir1: The direction register for the higher 16 pins.
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* @output: The output enable register.
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*/
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struct airoha_gpio_ctrl {
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struct gpio_chip gc;
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void __iomem *data;
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void __iomem *dir[2];
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void __iomem *output;
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};
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static struct airoha_gpio_ctrl *gc_to_ctrl(struct gpio_chip *gc)
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{
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return container_of(gc, struct airoha_gpio_ctrl, gc);
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}
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static int airoha_dir_set(struct gpio_chip *gc, unsigned int gpio,
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int val, int out)
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{
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struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
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u32 dir = ioread32(ctrl->dir[gpio / 16]);
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u32 output = ioread32(ctrl->output);
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u32 mask = BIT((gpio % 16) * 2);
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if (out) {
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dir |= mask;
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output |= BIT(gpio);
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} else {
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dir &= ~mask;
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output &= ~BIT(gpio);
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}
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iowrite32(dir, ctrl->dir[gpio / 16]);
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if (out)
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gc->set(gc, gpio, val);
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iowrite32(output, ctrl->output);
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return 0;
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}
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static int airoha_dir_out(struct gpio_chip *gc, unsigned int gpio,
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int val)
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{
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return airoha_dir_set(gc, gpio, val, 1);
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}
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static int airoha_dir_in(struct gpio_chip *gc, unsigned int gpio)
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{
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return airoha_dir_set(gc, gpio, 0, 0);
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}
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static int airoha_get_dir(struct gpio_chip *gc, unsigned int gpio)
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{
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struct airoha_gpio_ctrl *ctrl = gc_to_ctrl(gc);
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u32 dir = ioread32(ctrl->dir[gpio / 16]);
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u32 mask = BIT((gpio % 16) * 2);
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return (dir & mask) ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
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}
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static int airoha_gpio_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct airoha_gpio_ctrl *ctrl;
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int err;
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ctrl = devm_kzalloc(dev, sizeof(*ctrl), GFP_KERNEL);
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if (!ctrl)
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return -ENOMEM;
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ctrl->data = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(ctrl->data))
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return PTR_ERR(ctrl->data);
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ctrl->dir[0] = devm_platform_ioremap_resource(pdev, 1);
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if (IS_ERR(ctrl->dir[0]))
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return PTR_ERR(ctrl->dir[0]);
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ctrl->dir[1] = devm_platform_ioremap_resource(pdev, 2);
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if (IS_ERR(ctrl->dir[1]))
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return PTR_ERR(ctrl->dir[1]);
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ctrl->output = devm_platform_ioremap_resource(pdev, 3);
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if (IS_ERR(ctrl->output))
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return PTR_ERR(ctrl->output);
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err = bgpio_init(&ctrl->gc, dev, 4, ctrl->data, NULL,
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NULL, NULL, NULL, 0);
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if (err)
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return dev_err_probe(dev, err, "unable to init generic GPIO");
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ctrl->gc.ngpio = AIROHA_GPIO_MAX;
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ctrl->gc.owner = THIS_MODULE;
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ctrl->gc.direction_output = airoha_dir_out;
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ctrl->gc.direction_input = airoha_dir_in;
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ctrl->gc.get_direction = airoha_get_dir;
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return devm_gpiochip_add_data(dev, &ctrl->gc, ctrl);
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}
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static const struct of_device_id airoha_gpio_of_match[] = {
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{ .compatible = "airoha,en7523-gpio" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, airoha_gpio_of_match);
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static struct platform_driver airoha_gpio_driver = {
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.driver = {
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.name = "airoha-gpio",
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.of_match_table = airoha_gpio_of_match,
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},
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.probe = airoha_gpio_probe,
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};
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module_platform_driver(airoha_gpio_driver);
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MODULE_DESCRIPTION("Airoha GPIO support");
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MODULE_AUTHOR("John Crispin <john@phrozen.org>");
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MODULE_LICENSE("GPL v2");
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