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ab7cabd09d
Compile-tested on: ramips/mt7621, x86/64. Run-tested on: ramips/mt7621. Signed-off-by: Stijn Segers <foss@volatilesystems.org>
88 lines
2.5 KiB
Diff
88 lines
2.5 KiB
Diff
From 0c8d249a70818f4f8e0d5543dc7157dfd8a5265e Mon Sep 17 00:00:00 2001
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From: Ryder Lee <ryder.lee@mediatek.com>
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Date: Wed, 20 Dec 2017 16:04:24 +0800
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Subject: [PATCH 220/224] arm64: dts: mt7622: add SATA device nodes
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This patch adds SATA support fot MT7622.
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Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
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Signed-off-by: Sean Wang <sean.wang@mediatek.com>
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---
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arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 ++++++
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arch/arm64/boot/dts/mediatek/mt7622.dtsi | 40 ++++++++++++++++++++++++++++
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2 files changed, 48 insertions(+)
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--- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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+++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
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@@ -323,6 +323,14 @@
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status = "okay";
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};
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+&sata {
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+ status = "okay";
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+};
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+
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+&sata_phy {
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+ status = "okay";
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+};
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+
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&spi0 {
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pinctrl-names = "default";
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pinctrl-0 = <&spic0_pins>;
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--- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
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@@ -9,6 +9,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt7622-clk.h>
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+#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/mt7622-power.h>
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#include <dt-bindings/reset/mt7622-reset.h>
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#include <dt-bindings/thermal/thermal.h>
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@@ -616,6 +617,45 @@
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};
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};
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+ sata: sata@1a200000 {
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+ compatible = "mediatek,mt7622-ahci",
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+ "mediatek,mtk-ahci";
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+ reg = <0 0x1a200000 0 0x1100>;
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+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "hostc";
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+ clocks = <&pciesys CLK_SATA_AHB_EN>,
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+ <&pciesys CLK_SATA_AXI_EN>,
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+ <&pciesys CLK_SATA_ASIC_EN>,
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+ <&pciesys CLK_SATA_RBC_EN>,
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+ <&pciesys CLK_SATA_PM_EN>;
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+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
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+ phys = <&sata_port PHY_TYPE_SATA>;
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+ phy-names = "sata-phy";
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+ ports-implemented = <0x1>;
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+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
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+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
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+ <&pciesys MT7622_SATA_PHY_SW_RST>,
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+ <&pciesys MT7622_SATA_PHY_REG_RST>;
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+ reset-names = "axi", "sw", "reg";
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+ mediatek,phy-mode = <&pciesys>;
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+ status = "disabled";
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+ };
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+
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+ sata_phy: sata-phy@1a243000 {
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+ compatible = "mediatek,generic-tphy-v1";
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+ #address-cells = <2>;
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+ #size-cells = <2>;
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+ ranges;
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+ status = "disabled";
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+
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+ sata_port: sata-phy@1a243000 {
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+ reg = <0 0x1a243000 0 0x0100>;
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+ clocks = <&topckgen CLK_TOP_ETH_500M>;
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+ clock-names = "ref";
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+ #phy-cells = <1>;
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+ };
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+ };
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+
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ethsys: syscon@1b000000 {
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compatible = "mediatek,mt7622-ethsys",
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"syscon";
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