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1199a91095
Refreshed patches. The following patches were upstreamed and have been deleted: * target/linux/lantiq/patches-4.14/0025-MIPS-lantiq-gphy-Remove-reboot-remove-reset-asserts.patch * target/linux/generic/pending-4.14/101-clocksource-mips-gic-timer-fix-clocksource-counter-w.patch * target/linux/generic/pending-4.14/103-MIPS-c-r4k-fix-data-corruption-related-to-cache-coherence.patch * target/linux/generic/pending-4.14/181-net-usb-add-lte-modem-wistron-neweb-d18q1.patch Compile-tested: ramips/mt7621, x86/64 Run-tested: ramips/mt7621 Signed-off-by: Stijn Segers <foss@volatilesystems.org>
127 lines
4.0 KiB
Diff
127 lines
4.0 KiB
Diff
From eddd13215d0f2b549ebc5f0e8796d5b1231f90a0 Mon Sep 17 00:00:00 2001
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From: Sham Muthayyan <smuthayy@codeaurora.org>
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Date: Tue, 19 Jul 2016 19:58:22 +0530
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Subject: PCI: qcom: Fixed IPQ806x PCIE init changes
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Change-Id: Ic319b1aec27a47809284759f8fcb6a8815b7cf7e
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Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
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---
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drivers/pci/host/pcie-qcom.c | 62 +++++++++++++++++++++++++++++++++++++-------
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1 file changed, 53 insertions(+), 9 deletions(-)
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--- a/drivers/pci/dwc/pcie-qcom.c
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+++ b/drivers/pci/dwc/pcie-qcom.c
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@@ -52,7 +52,13 @@
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#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
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#define PCIE20_PARF_PHY_CTRL 0x40
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+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
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+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
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+
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#define PCIE20_PARF_PHY_REFCLK 0x4C
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+#define REF_SSP_EN BIT(16)
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+#define REF_USE_PAD BIT(12)
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+
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#define PCIE20_PARF_DBI_BASE_ADDR 0x168
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#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C
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#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
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@@ -83,6 +89,18 @@
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#define DBI_RO_WR_EN 1
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#define PERST_DELAY_US 1000
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+/* PARF registers */
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+#define PCIE20_PARF_PCS_DEEMPH 0x34
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+#define PCS_DEEMPH_TX_DEEMPH_GEN1(x) (x << 16)
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+#define PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(x) (x << 8)
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+#define PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(x) (x << 0)
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+
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+#define PCIE20_PARF_PCS_SWING 0x38
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+#define PCS_SWING_TX_SWING_FULL(x) (x << 8)
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+#define PCS_SWING_TX_SWING_LOW(x) (x << 0)
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+
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+#define PCIE20_PARF_CONFIG_BITS 0x50
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+#define PHY_RX0_EQ(x) (x << 24)
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#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
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#define SLV_ADDR_SPACE_SZ 0x10000000
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@@ -102,6 +120,7 @@ struct qcom_pcie_resources_2_1_0 {
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struct regulator *vdda;
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struct regulator *vdda_phy;
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struct regulator *vdda_refclk;
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+ uint8_t phy_tx0_term_offset;
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};
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struct qcom_pcie_resources_1_0_0 {
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@@ -179,6 +198,16 @@ struct qcom_pcie {
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#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
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+static inline void
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+writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
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+{
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+ u32 val = readl(addr);
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+
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+ val &= ~clear_mask;
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+ val |= set_mask;
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+ writel(val, addr);
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+}
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+
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static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
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{
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gpiod_set_value_cansleep(pcie->reset, 1);
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@@ -280,6 +309,10 @@ static int qcom_pcie_get_resources_2_1_0
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if (IS_ERR(res->ext_reset))
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return PTR_ERR(res->ext_reset);
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+ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
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+ &res->phy_tx0_term_offset))
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+ res->phy_tx0_term_offset = 0;
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+
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res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
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return PTR_ERR_OR_ZERO(res->phy_reset);
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}
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@@ -309,7 +342,6 @@ static int qcom_pcie_init_2_1_0(struct q
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struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
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struct dw_pcie *pci = pcie->pci;
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struct device *dev = pci->dev;
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- u32 val;
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int ret;
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ret = reset_control_assert(res->ahb_reset);
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@@ -378,15 +410,26 @@ static int qcom_pcie_init_2_1_0(struct q
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goto err_deassert_ahb;
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}
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- /* enable PCIe clocks and resets */
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- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
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- val &= ~BIT(0);
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- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
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-
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- /* enable external reference clock */
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- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
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- val |= BIT(16);
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- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
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+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL, BIT(0), 0);
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+
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+ /* Set Tx termination offset */
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+ writel_masked(pcie->parf + PCIE20_PARF_PHY_CTRL,
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+ PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK,
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+ PHY_CTRL_PHY_TX0_TERM_OFFSET(res->phy_tx0_term_offset));
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+
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+ /* PARF programming */
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+ writel(PCS_DEEMPH_TX_DEEMPH_GEN1(0x18) |
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+ PCS_DEEMPH_TX_DEEMPH_GEN2_3_5DB(0x18) |
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+ PCS_DEEMPH_TX_DEEMPH_GEN2_6DB(0x22),
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+ pcie->parf + PCIE20_PARF_PCS_DEEMPH);
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+ writel(PCS_SWING_TX_SWING_FULL(0x78) |
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+ PCS_SWING_TX_SWING_LOW(0x78),
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+ pcie->parf + PCIE20_PARF_PCS_SWING);
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+ writel(PHY_RX0_EQ(0x4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
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+
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+ /* Enable reference clock */
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+ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
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+ REF_USE_PAD, REF_SSP_EN);
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ret = reset_control_deassert(res->phy_reset);
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if (ret) {
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